| Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems H Cherupalli, R Kumar, J Sartori Proceedings of the 43rd International Symposium on Computer Architecture …, 2016 | 59 | 2016 |
| Bespoke processors for applications with ultra-low area and power constraints H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori Proceedings of the 44th Annual International Symposium on Computer …, 2017 | 40 | 2017 |
| Determining Application-specific Peak Power and Energy Requirements for ultra-low-power Processors H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori Proceedings of the 23rd International Conference on Architectural Support …, 2017 | 37 | 2017 |
| Software-based gate-level information flow security for IoT systems H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 17 | 2017 |
| Graph-based dynamic analysis: Efficient characterization of dynamic timing and activity distributions H Cherupalli, J Sartori 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 729-735, 2015 | 15 | 2015 |
| Enabling effective module-oblivious power gating for embedded processors H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori 2017 IEEE International symposium on high performance computer architecture …, 2017 | 12 | 2017 |
| Scalable n-worst algorithms for dynamic timing and activity analysis H Cherupalli, J Sartori 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 585-592, 2017 | 9 | 2017 |
| Graph based dynamic timing and activity analysis H Cherupalli, J Sartori US Patent App. 15/800,330, 2018 | 7 | 2018 |
| Automated error prediction for approximate sequential circuits A Kapare, H Cherupalli, J Sartori 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 5 | 2016 |
| Constrained conservative state symbolic co-analysis for ultra-low-power embedded systems S Hegde, S Sethumurugan, H Cherupalli, H Duwe, J Sartori Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 3 | 2021 |
| A scalable symbolic simulation tool for low power embedded systems S Sethumurugan, S Hegde, H Cherupalli, J Sartori Proceedings of the 59th ACM/IEEE Design Automation Conference, 175-180, 2022 | 2 | 2022 |
| Application-specific processor generation from general purpose processors H Cherupalli, R Kumar, J Sartori US Patent 10,671,774, 2020 | 2 | 2020 |
| Bespoke processors for applications with ultra-low area and power constraints H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori IEEE Micro 38 (3), 32-39, 2018 | 2 | 2018 |
| Gate activity analysis H Cherupalli, R Kumar, J Sartori US Patent 11,210,439, 2021 | 1 | 2021 |
| Power savings in processors J Sartori, H Cherupalli, R Kumar | | 2022 |
| Power savings in processors H Cherupalli, R Kumar, J Sartori US Patent 11,301,030, 2022 | | 2022 |
| Gate activity analysis J Sartori, H Cherupalli, R Kumar | | 2021 |
| Gate-level information flow security J Sartori, H Cherupalli, HJ Duwe, R Kumar | | 2021 |
| Gate-level information flow security H Cherupalli, R Kumar, J Sartori, H Duwe US Patent 11,210,402, 2021 | | 2021 |
| Power savings in processors H Cherupalli, R Kumar, J Sartori US Patent 10,866,630, 2020 | | 2020 |
John SartoriProfessor of Electrical and Computer Engineering, University of MinnesotaEmail được xác minh tại umn.edu