| A TDMA-based arbitration scheme for mixed-criticality multicore platforms B Cilku, A Crespo, P Puschner, J Coronel, S Peiro 2015 International Conference on Event-based Control, Communication, and …, 2015 | 28 | 2015 |
| Link reliability analysis in ad hoc networks T Dimitar, F Sonja, C Bekim, G Aksenti Proceedings of XII telekomunikacioni forum TELFOR, 23-25, 2004 | 15 | 2004 |
| A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking B Cilku, D Prokesch, P Puschner 2015 IEEE International Symposium on Object/Component/Service-Oriented Real …, 2015 | 14 | 2015 |
| Grid computing implementation in Ad hoc networks A Grnarov, B Cilku, I Miskovski, S Filiposka, D Trajanov Advances in computer and information sciences and engineering, 196-201, 2008 | 14 | 2008 |
| A dual-layer bus arbiter for mixed-criticality systems with hypervisors B Cilku, B Frömel, P Puschner 2014 12th IEEE International Conference on Industrial Informatics (INDIN …, 2014 | 12 | 2014 |
| Towards a time-predictable hierarchical memory architecture-prefetching options to be explored B Cilku, P Puschner 2010 13th IEEE International Symposium on Object/Component/Service-Oriented …, 2010 | 11 | 2010 |
| Towards temporal and spatial isolation in memory hierarchies for mixed-criticality systems with hypervisors B Cilku, P Puschner Proc. ReTiMiCS, RTCSA, 25-28, 2013 | 10 | 2013 |
| A memory arbitration scheme for mixed-criticality multocore platforms B Cilku, A Crespo, P Puschner, J Coronel, S Peiro Proc. 2nd Workshop on Mixed Criticality Systems (WMC), RTSS, 27-32, 2014 | 5 | 2014 |
| Improving performance of single-path code through a time-predictable memory hierarchy B Cilku, W Puffitsch, D Prokesch, M Schoeberl, P Puschner 2017 IEEE 20th International Symposium on Real-Time Distributed Computing …, 2017 | 4 | 2017 |
| New algorithms for efficient scheduling in Grid Ad-Hoc networks B Cilku, A Grnarov Proceedings of the ITI 2009 31st International Conference on Information …, 2009 | 4 | 2009 |
| Constructing time-predictable MPSoCs: Avoid conflicts in temporal control P Puschner, B Cilku, D Prokesch 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core …, 2016 | 3 | 2016 |
| Aligning Single Path Loops to Reduce the Number of Capacity Cache Misses B Cilku, R Kammerer, P Puschner 6th International Workshop on Compositional Theory and Technology for Real …, 2013 | 3 | 2013 |
| Best practice for caching of single-path code M Schoeberl, B Cilku, D Prokesch, P Puschner Open Access Series in Informatics 57, 2017 | 2 | 2017 |
| Designing a time predictable memory hierarchy for single-path code B Cilku, P Puschner ACM SIGBED Review 12 (2), 16-21, 2015 | 1 | 2015 |
| Using a Local Prefetch Strategy to Obtain Temporal Time Predictability B Cilku, P Puschner | 1 | 2011 |
| Time-predictable memory hierarchy B Chilku Technische Universität Wien, 2018 | | 2018 |
| OASIcs, Volume 57, WCET'17, Complete Volume}} J Reineke, B Rouxel, I Puaut, M Schoeberl, B Cilku, D Prokesch, ... 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017 …, 2017 | | 2017 |
| 17th International Workshop on Worst-case Execution Time Analysis: WCET 2017, June 27, 2017, Dubrovnik, Croatia J Reineke Schloss Dagstuhl-Leibniz-Zentrum für Informatik GmbH, Dagstuhl Publishing, 2017 | | 2017 |
| Usability constraints of grid in ad hoc networks B Cilku, A Grnarov, A Abazi 2009 International Conference on Innovations in Information Technology (IIT …, 2009 | | 2009 |
| Ad Hoc Networks Routing Protocols Efficiency With Respect To Connection Availability T Dimitar, F Sonja, C Bekim, A Grnarov | | |
Peter P. PuschnerProfessor of Informatics, TU WienEmail được xác minh tại vmars.tuwien.ac.at