Arrangements for automatic re-legging of transistors S Wimer
US Patent 7,079,989, 2006
199 2006 Optimal chaining of CMOS transistors in a functional cell S Wimer, RY Pinter, JA Feldman
IEEE transactions on computer-aided design of integrated circuits and …, 1987
143 1987 Optimal aspect ratios of building blocks in VLSI S Wimer, I Koren, I Cederbaum
IEEE transactions on computer-aided design of integrated circuits and …, 1989
121 1989 Floorplans, planar graphs, and layouts S Wimer, I Koren, I Cederbaum
IEEE Transactions on Circuits and Systems 35 (3), 267-278, 1988
115 1988 Design flow for flip-flop grouping in data-driven clock gating S Wimer, I Koren
IEEE Transactions on very large scale integration (VLSI) systems 22 (4), 771-778, 2013
95 2013 The optimal fan-out of clock network for power minimization by adaptive gating S Wimer, I Koren
IEEE transactions on very large scale integration (VLSI) systems 20 (10 …, 2011
88 2011 Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation R Bar-Yehuda, JA Feldman, RY Pinter, S Wimer
IEEE transactions on computer-aided design of integrated circuits and …, 1989
48 1989 The Wiener maximum quadratic assignment problem E Cela, NS Schmuck, S Wimer, GJ Woeginger
Discrete Optimization 8 (3), 411-416, 2011
45 2011 A cost effective centralized adaptive routing for networks-on-chip R Manevich, I Cidon, A Kolodny, S Wimer
2011 14th Euromicro Conference on Digital System Design, 39-46, 2011
42 2011 Timing-aware power-optimal ordering of signals K Moiseev, A Kolodny, S Wimer
ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (4 …, 2008
35 2008 A look-ahead clock gating based on auto-gated flip-flops S Wimer, A Albahari
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (5), 1465-1472, 2014
33 2014 Analysis of strategies for constructive general block placement S Wimer, I Koren
IEEE transactions on computer-aided design of integrated circuits and …, 1988
33 1988 Probability-driven multibit flip-flop integration with clock gating D Gluzer, S Wimer
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3 …, 2016
26 2016 System and method for generating a clock gating network for logic circuits S Wimer
US Patent App. 13/361,986, 2013
21 2013 Optimal bus sizing in migration of processor design S Wimer, S Michaely, K Moiseev, A Kolodny
IEEE Transactions on Circuits and Systems I: Regular Papers 53 (5), 1089-1100, 2006
21 2006 Opportunistic refreshing algorithm for eDRAM memories A Kazimirsky, S Wimer
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (11), 1921-1932, 2016
19 2016 Power-delay optimization in vlsi microprocessors by wire spacing K Moiseev, A Kolodny, S Wimer
ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (4 …, 2009
18 2009 A Low Energy and High Performance I Levi, A Albeck, A Fish, S Wimer
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (11), 3175-3183, 2014
17 2014 On optimal flip-flop grouping for VLSI power minimization S Wimer
Operations Research Letters 41 (5), 486-489, 2013
16 2013 Mixing drivers in clock-tree for power supply noise reduction Y Kaplan, S Wimer
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (5), 1382-1391, 2015
14 2015 