| A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning X Wu, V Saxena, K Zhu, S Balagopal IEEE Transactions on Circuits and Systems II: Express Briefs 62 (11), 1088-1092, 2015 | 189 | 2015 |
| Homogeneous spiking neuromorphic system for real-world pattern recognition X Wu, V Saxena, K Zhu IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5 (2 …, 2015 | 95 | 2015 |
| A CMOS spiking neuron for dense memristor-synapse connectivity for brain-inspired computing X Wu, V Saxena, K Zhu 2015 International Joint Conference on Neural Networks (IJCNN), 1-6, 2015 | 55 | 2015 |
| Compact Verilog-A modeling of silicon traveling-wave modulator for hybrid CMOS photonic circuit design K Zhu, V Saxena, W Kuang 2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014 | 38 | 2014 |
| Towards neuromorphic learning machines using emerging memory devices with brain-like energy efficiency V Saxena, X Wu, I Srivastava, K Zhu Journal of Low Power Electronics and Applications 8 (4), 34, 2018 | 36 | 2018 |
| Design Considerations for Traveling-Wave Modulator Based CMOS Photonic Transmitters K Zhu, V Saxena, X Wu, W Kuang IEEE Transactions on Circuits and Systems II: Express Briefs, 2015 | 35 | 2015 |
| A 3D-integrated 56 Gb/s NRZ/PAM4 reconfigurable segmented Mach-Zehnder modulator-based Si-photonics transmitter C Li, K Yu, J Rhim, K Zhu, N Qi, M Fiorentino, T Pinguet, M Peterson, ... 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and …, 2018 | 34 | 2018 |
| Energy-efficient CMOS memristive synapses for mixed-signal neuromorphic system-on-a-chip V Saxena, X Wu, K Zhu 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 26 | 2018 |
| Circuits to enable reconfigurability K Zhu, C Li, Z Zhu US Patent 9,973,218, 2018 | 19 | 2018 |
| Study of current saturation behaviors in dual direction SCR for ESD applications Y Han, B Song, S Dong, M Li, F Ma, M Miao, K Zhu Microelectronics Reliability 51 (2), 332-336, 2011 | 17 | 2011 |
| From Design to Test: A High-Speed PRBS K Zhu, V Saxena IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018 | 13 | 2018 |
| Investigation of pickup effect for multi-fingered ESD devices in 0.5 µm 5V/18V CDMOS process A Zhou, Y Wang, K Zhu, X Jin Electronics letters 48 (15), 911-913, 2012 | 12 | 2012 |
| A case study of problems in JEDEC HBM ESD test standard M Huo, Q Guo, Y Han, L Shen, Q Liu, B Song, Q Ma, K Zhu, Y Shen, X Du, ... IEEE Transactions on Device and Materials Reliability 9 (3), 361-366, 2009 | 11 | 2009 |
| Towards spiking neuromorphic system-on-a-chip with bio-plausible synapses using emerging devices V Saxena, X Wu, I Srivastava, K Zhu Proceedings of the 4th ACM International Conference on Nanoscale Computing …, 2017 | 10 | 2017 |
| Design analysis of a novel low triggering voltage dual direction SCR ESD device in 0.18 µm mixed mode RFCMOS technology K Zhu, Z Yu, S Dong, Y Han Chin J Semicond 29 (11), 2164-8, 2008 | 9* | 2008 |
| A novel integrated ultraviolet photodetector based on standard CMOS process H Wang, XL Jin, CP Chen, MF Tian, KH Zhu Chinese Physics B 24 (3), 038501, 2015 | 8* | 2015 |
| Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process F Ma, Y Han, B Song, S Dong, M Miao, J Zheng, J Wu, K Zhu Microelectronics Reliability 51 (12), 2124-2128, 2011 | 8 | 2011 |
| Modeling of MZM-based photonic link power budget K Zhu, C Li, N Qi, K Yu, M Fiorentino, R Beausoleil, V Saxena 2016 IEEE Optical Interconnects Conference (OI), 58-59, 2016 | 7 | 2016 |
| Design Analysis of a 12.5 GHz PLL in 130 nm SiGe BiCMOS Process K Zhu, V Saxena, X Wu, S Balagopal Microelectronics and Electron Devices (WMED), 2015 IEEE Workshop on, 2015 | 7 | 2015 |
| Compact MOS-triggered SCR with faster turn-on speed for ESD protection B Song, Y Han, S Dong, F Ma, M Li, M Miao, K Zhu Microelectronics Reliability 50 (9-11), 1393-1397, 2010 | 7 | 2010 |
Vishal SaxenaUniversity of DelawareEmail được xác minh tại udel.edu