| Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance D Garyfallou, S Simoglou, N Sketopoulos, C Antoniadis, CP Sotiriou, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (5), 962-972, 2021 | 26 | 2021 |
| Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation D Garyfallou, I Tsiokanos, N Evmorfopoulos, G Stamoulis, ... 21st International Symposium on Quality Electronic Design (ISQED), 225-230, 2020 | 23 | 2020 |
| Exploiting extended Krylov subspace for the reduction of regular and singular circuit models C Chatzigeorgiou, D Garyfallou, G Floros, N Evmorfopoulos, G Stamoulis 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 773-778, 2021 | 14 | 2021 |
| Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance D Garyfallou, A Vagenas, C Antoniadis, Y Massoud, G Stamoulis Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), 77-83, 2022 | 13 | 2022 |
| Heuristics to augment the performance of Tetris legalization: making a fast but inferior method competitive AN Dadaliaris, P Oikonomou, MG Koziri, E Nerantzaki, Y Hatzaras, ... Journal of Low Power Electronics 13 (2), 220-230, 2017 | 11 | 2017 |
| EVT-based worst case delay estimation under process variation C Antoniadis, D Garyfallou, N Evmorfopoulos, G Stamoulis Design, Automation & Test in Europe Conference & Exhibition (DATE), 1333-1338, 2018 | 10 | 2018 |
| A fast semi-analytical approach for transient electromigration analysis of interconnect trees using matrix exponential P Stoikos, G Floros, D Garyfallou, N Evmorfopoulos, G Stamoulis 28th Asia and South Pacific Design Automation Conference (ASP-DAC), 1-6, 2023 | 9 | 2023 |
| A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects D Garyfallou, C Antoniadis, N Evmorfopoulos, G Stamoulis 16th International Conference on Synthesis, Modeling, Analysis and …, 2019 | 9 | 2019 |
| A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPUs D Garyfallou, N Evmorfopoulos, G Stamoulis 15th International Conference on Synthesis, Modeling, Analysis and …, 2018 | 9 | 2018 |
| Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis GI Paliaroutis, P Tsoumanis, D Garyfallou, A Vagenas, N Evmorfopoulos, ... IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2023 | 3 | 2023 |
| Large scale circuit simulation exploiting combinatorial multigrid on massively parallel architectures D Garyfallou, N Evmorfopoulos, G Stamoulis 7th International Conference on Modern Circuits and Systems Technologies …, 2018 | 3 | 2018 |
| Reduction of large-scale RLCk models via low-rank balanced truncation C Giamouzis, D Garyfallou, A Vagenas, N Evmorfopoulos HETiA Emerging Tech Conference – Edge Intelligence (ETCEI) [arXiv preprint …, 2023 | 2 | 2023 |
| The Extended and Asymmetric Extended Krylov Subspace in Moment-Matching-Based Order Reduction of Large Circuit Models P Stoikos, D Garyfallou, G Floros, N Evmorfopoulos, G Stamoulis arXiv preprint arXiv:2204.02467, 2022 | 2 | 2022 |
| Frequency-Limited Reduction of RLCK Circuits via Second-Order Balanced Truncation O Axelou, D Garyfallou, G Floros SMACD/PRIME 2021; International Conference on SMACD and 16th Conference on …, 2021 | 2 | 2021 |
| Low-rank balanced truncation of RLCk models via frequency-aware rational Krylov-based projection C Giamouzis, D Garyfallou, G Stamoulis, N Evmorfopoulos 20th International Conference on Synthesis, Modeling, Analysis and …, 2024 | 1 | 2024 |
| Advanced gate-level glitch modeling using ANNs A Vagenas, D Garyfallou, N Evmorfopoulos, G Stamoulis Proceedings of the 61st ACM/IEEE Design Automation Conference, 1-6, 2024 | 1 | 2024 |
| Accelerated Recurrent Neural Network Dynamics for Time-Varying Lyapunov Equation Solving A Doumanis, D Gerontitis, D Garyfallou Panhellenic Conference on Electronics & Telecommunications (PACET), 1-4, 2024 | 1 | 2024 |
| Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential P Stoikos, G Floros, D Garyfallou, N Evmorfopoulos, G Stamoulis 19th International Conference on Synthesis, Modeling, Analysis and …, 2023 | 1 | 2023 |
| Novel techniques for timing analysis of VLSI circuits in advanced technology nodes D Garyfallou University of Thessaly, 2021 | 1 | 2021 |
| A gate-level SER estimation tool with event-driven dynamic timing and SET height consideration GI Paliaroutis, P Tsoumanis, D Garyfallou, A Vagenas, N Evmorfopoulos, ... IEEE Transactions on Device and Materials Reliability (TDMR), 2024 | | 2024 |
George StamoulisProfessor of Electrical and Computer Engineering, University of ThessalyEmail được xác minh tại uth.gr
