| Flexflow: A flexible dataflow accelerator architecture for convolutional neural networks W Lu, G Yan, J Li, S Gong, Y Han, X Li 2017 IEEE international symposium on high performance computer architecture …, 2017 | 427 | 2017 |
| DeepBurning: Automatic generation of FPGA-based learning accelerators for the neural network family Y Wang, J Xu, Y Han, H Li, X Li Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 273 | 2016 |
| Rt3d: Real-time 3-d vehicle detection in lidar point cloud for autonomous driving Y Zeng, Y Hu, S Liu, J Ye, Y Han, X Li, N Sun IEEE Robotics and Automation Letters 3 (4), 3434-3440, 2018 | 193 | 2018 |
| Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology X Zou, S Xu, X Chen, L Yan, Y Han Science China Information Sciences 64 (6), 160404, 2021 | 187 | 2021 |
| C-Brain: A deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization L Song, Y Wang, Y Han, X Zhao, B Liu, X Li Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 138 | 2016 |
| Exploring spatial-temporal multi-frequency analysis for high-fidelity and temporal-consistency video prediction B Jin, Y Hu, Q Tang, J Niu, Z Shi, Y Han, X Li Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern …, 2020 | 127 | 2020 |
| An abacus turn model for time/space-efficient reconfigurable routing B Fu, Y Han, J Ma, H Li, X Li Proceedings of the 38th annual international symposium on Computer …, 2011 | 123 | 2011 |
| See and think: Disentangling semantic scene completion S Liu, Y Hu, Y Zeng, Q Tang, B Jin, Y Han, X Li Advances in Neural Information Processing Systems 31, 2018 | 99 | 2018 |
| On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems L Zhang, Y Han, Q Xu, X wei Li, H Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (9 …, 2009 | 93 | 2009 |
| System-level hardware failure prediction using deep learning X Sun, K Chakrabarty, R Huang, Y Chen, B Zhao, H Cao, Y Han, X Liang, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 90 | 2019 |
| Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip C Liu, L Zhang, Y Han, X Li 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 357-362, 2011 | 82 | 2011 |
| Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology L Zhang, Y Han, Q Xu, X Li Proceedings of the conference on Design, automation and test in Europe, 891-896, 2008 | 82 | 2008 |
| Chipgpt: How far are we from natural language hardware design K Chang, Y Wang, H Ren, M Wang, S Liang, Y Han, H Li, X Li arXiv preprint arXiv:2305.14019, 2023 | 77 | 2023 |
| Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs Y Cheng, L Zhang, Y Han, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 239-249, 2012 | 74 | 2012 |
| Agileregulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture G Yan, Y Li, Y Han, X Li, M Guo, X Liang IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012 | 71 | 2012 |
| Wear rate leveling: Lifetime enhancement of PRAM with endurance variation J Dong, L Zhang, Y Han, Y Wang, X Li Proceedings of the 48th Design Automation Conference, 972-977, 2011 | 70 | 2011 |
| Design and analysis of energy-efficient dynamic range approximate logarithmic multipliers for machine learning P Yin, C Wang, H Waris, W Liu, Y Han, F Lombardi IEEE Transactions on Sustainable Computing 6 (4), 612-625, 2020 | 67 | 2020 |
| PIM-prune: Fine-grain DCNN pruning for crossbar-based process-in-memory architecture C Chu, Y Wang, Y Zhao, X Ma, S Ye, Y Hong, X Liang, Y Han, L Jiang 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 66 | 2020 |
| PIMSim: A flexible and detailed processing-in-memory simulator S Xu, X Chen, Y Wang, Y Han, X Qian, X Li IEEE Computer Architecture Letters 18 (1), 6-9, 2018 | 65 | 2018 |
| ZoneDefense: A fault-tolerant routing for 2-D meshes without virtual channels B Fu, Y Han, H Li, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (1), 113-126, 2013 | 59 | 2013 |
Xiaowei Li (李晓维)Institute of Computing Technology, Chinese Academy of SciencesEmail được xác minh tại ict.ac.cn