| Method of making multichip wafer level packages and computing systems incorporating same SK Chua, SW Low, YP Chia, MK Eng, YL Neo, SJ Boon, S Huang, ... US Patent 7,485,562, 2009 | 209* | 2009 |
| Packaged microelectronic components EM Koon, LS Waf, CM Yu, CY Poo, SB Leng, Z Wei US Patent 6,836,009, 2004 | 132 | 2004 |
| Castellation wafer level packaging of integrated circuit chips BS Jeung, CY Poo, LS Waf, EM Koon, CS Kwang, HS Wu, NY Loo, Z Wei US Patent 6,855,572, 2005 | 88 | 2005 |
| Multi-chip wafer level system packages and methods of forming same SK Chua, SW Low, YP Chia, MK Eng, YL Neo, SJ Boon, S Huang, ... US Patent 6,964,881, 2005 | 56 | 2005 |
| Semiconductor device with an electrically-coupled protection mechanism and associated systems, devices, and methods W Zhou, BK Street US Patent 10,475,771, 2019 | 31 | 2019 |
| A new variable-order singular boundary element for calculating stress intensity factors in three-dimensional elasticity problems W Zhou, KM Lim, KH Lee, AAO Tay International journal of solids and structures 42 (1), 159-185, 2005 | 31 | 2005 |
| A new variable‐order singular boundary element for two‐dimensional stress analysis KM Lim, KH Lee, AAO Tay, W Zhou International journal for numerical methods in engineering 55 (3), 293-316, 2002 | 31 | 2002 |
| Multichip wafer level packages and computing systems incorporating same SK Chua, SW Low, YP Chia, MK Eng, YL Neo, SJ Boon, S Huang, ... US Patent 7,087,992, 2006 | 30 | 2006 |
| Castellation wafer level packaging of integrated circuit chips SJ Boon, YP Chia, SW Low, MK Eng, SK Chua, SW Huang, YL Neo, ... US Patent 7,193,312, 2007 | 27 | 2007 |
| Methods for forming semiconductor device packages Z Ma, W Zhou, A Yu US Patent 9,202,714, 2015 | 25 | 2015 |
| Packaged microelectronic components EM Koon, LS Waf, CM Yu, CY Poo, SB Leng, Z Wei US Patent 7,195,957, 2007 | 23 | 2007 |
| Semiconductor die assemblies with heat sink and associated systems and methods W Zhou, Z Ma, A Yu US Patent 9,349,670, 2016 | 22 | 2016 |
| Studies on moisture-induced failures in ACF interconnection Z Wei, LS Waf, NY Loo, EM Koon, M Huang Electronics Packaging Technology Conference, 2002. 4th., 133-138, 2002 | 18 | 2002 |
| Methods of manufacturing multi-die semiconductor device packages and related assemblies W Zhou, A Yu, Z Ma, S Varghese, JS Hacker, BK Street, S Luo US Patent 9,865,578, 2018 | 17 | 2018 |
| Critical challenges with copper hybrid bonding for chip-to-wafer memory stacking W Zhou, M Kwon, Y Chiu, H Guo, B Bhushan, B Street, K Parekh, A Singh 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), 336-341, 2023 | 16 | 2023 |
| Semiconductor devices comprising protected side surfaces and related methods Z Ma, W Zhou, CC So, SL Ang, A Yu US Patent 9,786,643, 2017 | 14 | 2017 |
| Methods of processing wafer-level assemblies to reduce warpage, and related assemblies A Yu, W Zhou, Z Ma, BK Street US Patent 9,589,933, 2017 | 14 | 2017 |
| Semiconductor constructions having interconnect structures, methods of forming interconnect structures, and methods of forming semiconductor constructions Z Wei, C Poo US Patent App. 11/436,172, 2007 | 14 | 2007 |
| Lead frames, microelectronic devices with lead frames, and methods for manufacturing lead frames and microelectronic devices with lead frames W Zhou, BL Ser US Patent App. 11/507,718, 2008 | 9 | 2008 |
| Bond pad with micro-protrusions for direct metallic bonding A Yu, W Zhou, Z Ma US Patent App. 14/496,082, 2016 | 8 | 2016 |