| Mask assignment for multiple patterning lithography RS Abou Ghaida, KB Agarwal, LW Liebmann, SR Nassif US Patent 8,434,033, 2013 | 40 | 2013 |
| Multiple patterning layout decomposition for ease of conflict removal RS Abou Ghaida, KB Agarwal, LW Liebmann, SR Nassif US Patent 8,516,403, 2013 | 39 | 2013 |
| Resolving double patterning conflicts RS Abou Ghaida, KB Agarwal, IBM Corporation US Patent 20,130,007,674, 2013 | 39 | 2013 |
| Layout decomposition and legalization for double-patterning technology RS Ghaida, KB Agarwal, SR Nassif, X Yuan, LW Liebmann, P Gupta IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 35 | 2013 |
| Single-mask double-patterning lithography for reduced cost and improved overlay control RS Ghaida, G Torres, P Gupta IEEE Transactions on Semiconductor Manufacturing 24 (1), 93-103, 2010 | 35 | 2010 |
| Single-mask double-patterning lithography P Gupta, RS Ghaida US Patent 8,415,089, 2013 | 26 | 2013 |
| DRE: A framework for early co-evaluation of design rules, technology choices, and layout methodologies RS Ghaida, P Gupta IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 26 | 2012 |
| Design-overlay interactions in metal double patterning RS Ghaida, P Gupta Design for Manufacturability through Design-Process Integration III 7275 …, 2009 | 26 | 2009 |
| A novel methodology for triple/multiple-patterning layout decomposition RS Ghaida, KB Agarwal, LW Liebmann, SR Nassif, P Gupta Design for Manufacturability through Design-Process Integration VI 8327, 176-183, 2012 | 25 | 2012 |
| Electrical modeling of lithographic imperfections TB Chan, RS Ghaida, P Gupta 2010 23rd International Conference on VLSI Design, 423-428, 2010 | 23 | 2010 |
| A framework for early and systematic evaluation of design rules RS Ghaida, P Gupta Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 22 | 2009 |
| A framework for double patterning-enabled design RS Ghaida, KB Agarwal, SR Nassif, X Yuan, LW Liebmann, P Gupta 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 14-20, 2011 | 19 | 2011 |
| Framework for exploring the interaction between design rules and overlay control RS Ghaida, M Gupta, P Gupta Journal of Micro/Nanolithography, MEMS, and MOEMS 12 (3), 033014-033014, 2013 | 17 | 2013 |
| A framework for exploring the interaction between design rules and overlay control RS Ghaida, M Gupta, P Gupta Metrology, Inspection, and Process Control for Microlithography 8681, 86810C, 2013 | 17 | 2013 |
| Within-layer overlay impact for design in metal double patterning RS Ghaida, P Gupta IEEE Transactions on Semiconductor Manufacturing 23 (3), 381-390, 2010 | 17 | 2010 |
| Random yield prediction based on a stochastic layout sensitivity model RS Ghaida, K Doniger, P Zarkesh-Ha IEEE transactions on semiconductor manufacturing 22 (3), 329-337, 2009 | 17 | 2009 |
| Comprehensive die-level assessment of design rules and layouts RS Ghaida, Y Badr, M Gupta, N Jin, P Gupta 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 61-66, 2014 | 13 | 2014 |
| A methodology for the early exploration of design rules for multiple-patterning technologies RS Ghaida, T Sahu, P Kulkarni, P Gupta Proceedings of the International Conference on Computer-Aided Design, 50-56, 2012 | 13 | 2012 |
| A layout sensitivity model for estimating electromigration-vulnerable narrow interconnects RS Ghaida, P Zarkesh-Ha Journal of Electronic Testing 25, 67-77, 2009 | 13 | 2009 |
| Layout pattern correction for integrated circuits R Abou Ghaida, A Mohyeldin, P Pathak, S Muddu, V Dai, L Capodieci US Patent 8,898,606, 2014 | 12 | 2014 |
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