Gate-all-around nanowire MOSFET and method of formation K Cheng, BB Doris, P Hashemi, A Khakifirooz, A Reznicek
US Patent 8,969,934, 2015
283 2015 Integrated circuit having MOSFET with embedded stressor and method to fabricate same K Cheng, P Hashemi, A Khakifirooz, A Reznicek
US Patent 8,975,697, 2015
276 2015 High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET K Cheng, A Khakifirooz, N Loubet, S Luning, T Nagumo, M Vinet, Q Liu, ...
2012 International Electron Devices Meeting, 18.1. 1-18.1. 4, 2012
122 2012 Nanowire transistor structures with merged source/drain regions using auxiliary pillars P Hashemi, A Khakifirooz, A Reznicek
US Patent 9,257,527, 2016
115 2016 Demonstration of nanosecond operation in stochastic magnetic tunnel junctions C Safranski, J Kaiser, P Trouilloud, P Hashemi, G Hu, JZ Sun
Nano letters 21 (5), 2040-2045, 2021
96 2021 Fabrication of nano-sheet transistors with different threshold voltages K Balakrishnan, K Cheng, P Hashemi, A Reznicek
US Patent 9,653,289, 2017
94 2017 Stacked complementary fets featuring vertically stacked horizontal nanowires K Balakrishnan, K Cheng, P Hashemi, A Reznicek
US Patent 9,837,414, 2017
90 2017 Gate-all-around n-MOSFETs with uniaxial tensile strain-induced performance enhancement scalable to sub-10-nm nanowire diameter P Hashemi, L Gomez, JL Hoyt
IEEE Electron Device Letters 30 (4), 401-403, 2009
84 2009 FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
73 2016 Vertical transistor with air gap spacers K Balakrishnan, K Cheng, P Hashemi, A Reznicek
US Patent 9,443,982, 2016
70 2016 Perfectly symmetric gate-all-around FET on suspended nanowire K Cheng, P Hashemi, A Khakifirooz, A Reznicek
US Patent 9,853,166, 2017
64 2017 Contact formation to 3D monolithic stacked FinFETs K Cheng, P Hashemi, A Khakifirooz, A Reznicek
US Patent 9,659,963, 2017
64 2017 Replacement III-V or germanium nanowires by unilateral confined epitaxial growth K Balakrishnan, K Cheng, P Hashemi, A Reznicek
US Patent 9,570,551, 2017
64 2017 Enhanced hole transport in short-channel strained-SiGe p-MOSFETs L Gomez, P Hashemi, JL Hoyt
IEEE transactions on electron devices 56 (11), 2644-2651, 2009
64 2009 Vertically stacked nFET and pFET with dual work function A Reznicek, T Ando, J Zhang, CH Lee, P Hashemi
US Patent 10,546,925, 2020
63 2020 Channel-last replacement metal-gate vertical field effect transistor K Balakrishnan, K Cheng, P Hashemi, A Reznicek
US Patent 9,525,064, 2016
63 2016 Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance K Balakrishnan, K Cheng, P Hashemi, A Reznicek
US Patent 9,773,913, 2017
62 2017 Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction K Cheng, P Hashemi, A Khakifirooz, A Reznicek
US Patent 10,396,152, 2019
61 2019 Ultrathin Strained-Ge Channel P-MOSFETs With High- P Hashemi, W Chern, HS Lee, JT Teherani, Y Zhu, J Gonsalvez, ...
IEEE electron device letters 33 (7), 943-945, 2012
60 2012 Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications G Hu, JJ Nowak, MG Gottwald, SL Brown, B Doris, CP D’Emic, P Hashemi, ...
2019 IEEE International Electron Devices Meeting (IEDM), 2.6. 1-2.6. 4, 2019
58 2019 
Ammar NayfehProfessor in Electrical Engineering Khalifa UniversityEmail được xác minh tại ku.ac.ae