| VLSI implementation of parallel CRC using pipelining, unfolding and retiming S Singh, S Sujana, I Babu, K Latha IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) 2 (5), 66-72, 2013 | 18 | 2013 |
| Design and implementation of a low-power, high-speed comparator V Deepika, S Singh Procedia Materials Science 10, 314-322, 2015 | 14 | 2015 |
| Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip S Singh, J Ravindra, BR Naik 2016 International SoC Design Conference (ISOCC), 5-6, 2016 | 10 | 2016 |
| Proffering secure energy aware network-on-chip (Noc) using incremental cryptogine S Singh, JVR Ravindra, BR Naik Sustainable Computing: Informatics and Systems 35, 100682, 2022 | 4 | 2022 |
| RETRACTED: Design and implementation of network‐on‐chip router using multi‐priority based iterative round‐robin matching with slip S Singh, JVR Ravindra, BR Naik Transactions on Emerging Telecommunications Technologies 35 (10), e4514, 2024 | 3 | 2024 |
| Design of Pseudo-Random Number Generator Using Non-Linear Feedback Shift Register K Vooke, NK Toramamidi, KK Thodeti, S Singh 2022 First International Conference on Electrical, Electronics, Information …, 2022 | 3 | 2022 |
| Design of PUF Based Chaotic Random Number Generator UK Anchana, M Mogireddy, E Kadavergu, S Singh 2023 Second International Conference on Electrical, Electronics, Information …, 2023 | 2 | 2023 |
| Design And Analysis Of Physical Unclonable Function UK Anchana, S Singh, M Mogireddy, E Kadavergu 2023 2nd International Conference for Innovation in Technology (INOCON), 1-4, 2023 | 2 | 2023 |
| Design and FPGA Implementation of Matrix Multiplier Using DEMUX-RCA-Based Vedic Multiplier BY Kumar, S Kharwar, S Singh, MKA Mohammed, M Dauwed International Conference on Emerging Technologies and Intelligent Systems …, 2022 | 2 | 2022 |
| Power and Area Optimized FRA-CSLA for High-Speed NoC Applications S Singh, JVR Ravindra, B Rajenda Naik International Journal of Advanced Trends in Computer Science and Engineering …, 2019 | 2 | 2019 |
| Prediction of Intermittent Failure by Presage Debacle Model in Network on Chip S Singh, JVR Ravindra, BR Naik International Journal of Computer Network and Information Security 14 (4), 75, 2022 | 1 | 2022 |
| Design of an Energy efficiency Comparator using Dynamic Cancellation V Deepika, S Singh 2021 IEEE 2nd International Conference on Applied Electromagnetics, Signal …, 2021 | 1 | 2021 |
| LFMAC-Logic encryption of low power full adder with Multiplier and Accumulator as application LS Charan, S Singh 2021 IEEE Region 10 Symposium (TENSYMP), 1-4, 2021 | 1 | 2021 |
| Design & Comparison of 32-bit CSLA with Hybrid Logic S Kharwar, S Singh 2021 International Conference on Simulation, Automation & Smart …, 2021 | 1 | 2021 |
| Area and Power Efficient Self-Checking Modulo 2n+ 1 Multiplier B Mounika, S Singh International Journal of Computer Applications 76 (5), 2013 | 1 | 2013 |
| High speed ultra-low-lower lulse-triggered JLFET Flip-Flop S Kumar, M Panchore, S Singh, J Singh Modern Physics Letters B 38 (10), 2450068, 2024 | | 2024 |
| Efficient Realization of XOR PUF using GDI Technique in 4T/Cell Amplifier Chain G Sneha, S Sreeja, G Ganesh, S Singh 2023 4th IEEE Global Conference for Advancement in Technology (GCAT), 1-7, 2023 | | 2023 |
| Low‐Noise Amplifiers J Priya, S Singh, B Kumar RF Circuits for 5G Applications: Designing with mmWave Circuitry, 73-105, 2023 | | 2023 |
| Design and Implementation of Comparator Using GDI Decoder S Singh, T Akankhsa, Y Vamshi, S Munratiwar, MV Jayanth Advances in Signal Processing, Embedded Systems and IoT: Proceedings of …, 2023 | | 2023 |
| Design and Analysis of Three Operand Binary Adder V Surigi, B Koppunuri, A Chandrakala, S Signh 2023 Second International Conference on Electrical, Electronics, Information …, 2023 | | 2023 |
