| Spintronics: A contemporary review of emerging electronics devices VK Joshi Engineering science and technology, an international journal 19 (3), 1503-1513, 2016 | 285 | 2016 |
| Spintronic devices: a promising alternative to CMOS devices P Barla, VK Joshi, S Bhat Journal of Computational Electronics 20 (2), 805-837, 2021 | 211 | 2021 |
| From MTJ device to hybrid CMOS/MTJ circuits: A review VK Joshi, P Barla, S Bhat, BK Kaushik IEEE Access 8, 194105-194146, 2020 | 74 | 2020 |
| A novel low power and reduced transistor count magnetic arithmetic logic unit using hybrid STT-MTJ/CMOS circuit P Barla, VK Joshi, S Bhat IEEE Access 8, 6876-6889, 2020 | 35 | 2020 |
| Design and analysis of LIM hybrid MTJ/CMOS logic gates P Barla, D Shet, VK Joshi, S Bhat 2020 5th International Conference on Devices, Circuits and Systems (ICDCS …, 2020 | 18 | 2020 |
| A novel self write-terminated driver for hybrid STT-MTJ/CMOS LIM structure P Barla, VK Joshi, S Bhat Ain Shams Engineering Journal 12 (2), 1839-1847, 2021 | 15 | 2021 |
| Design and analysis of SHE-assisted STT MTJ/CMOS logic gates P Barla, VK Joshi, S Bhat Journal of Computational Electronics 20 (5), 1964-1976, 2021 | 14 | 2021 |
| Comparative study of 7T, 8T, 9T and 10T SRAM with conventional 6T SRAM cell using 180 nm technology VK Joshi, HC Lobo Advanced Computing and Communication Technologies, 25-40, 2016 | 13 | 2016 |
| Design of high speed carry select adder using modified parallel prefix adder AR Hebbar, P Srivastava, VK Joshi Procedia computer science 143, 317-324, 2018 | 11 | 2018 |
| Field-free switching of VG-SOT-pMTJ device through the interplay of SOT, exchange bias, and VCMA effects S Alla, V Kumar Joshi, S Bhat Journal of Applied Physics 134 (1), 2023 | 9 | 2023 |
| A comparative study of NC and PP-SRAM cells with 6T SRAM cell using 45nm CMOS technology VK Joshi, S Borkar 2016 International Conference on Advances in Electrical, Electronic and …, 2016 | 8 | 2016 |
| Voltage-Gated Spin-Orbit Torque Magnetic Tunnel Junction model analysis S Alla, VK Joshi, S Bhat 2022 International Conference on Distributed Computing, VLSI, Electrical …, 2022 | 6 | 2022 |
| Design of a novel non‐volatile hybrid spintronic true random number generator S Jape, VK Joshi, P Barla International Journal of Circuit Theory and Applications, 2022 | 4 | 2022 |
| A Novel Auto-Write-Stopping Circuit for SHE+ STT-MTJ/CMOS Hybrid ALU P Barla, VK Joshi, S Bhat IEEE Transactions on Electron Devices 69 (4), 1683-1690, 2022 | 3 | 2022 |
| Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure P Barla, VK Joshi, S Bhat Journal of Circuits, Systems and Computers, 2250146, 2022 | 3 | 2022 |
| DRV evaluation of 6T SRAM cell using efficient optimization techniques VK Joshi, C Nayak Active and Passive Electronic Components 2018, 2018 | 3 | 2018 |
| A Fully Non-Volatile Reconfigurable Magnetic Arithmetic Logic Unit Based on Majority Logic S Rangaprasad, VK Joshi IEEE Access 11, 118944-118961, 2023 | 2 | 2023 |
| Design and Analysis of Self-write-terminated Hybrid STT-MTJ/CMOS Logic Gates using LIM Architecture P Barla, VK Joshi, S Bhat 2021 IEEE International Conference on Distributed Computing, VLSI …, 2021 | 2 | 2021 |
| Design and evaluation of hybrid SHE+ STT-MTJ/CMOS full adder based on LIM architecture P Barla, VK Joshi, S Bhat IOP Conference Series: Materials Science and Engineering 1187 (1), 012015, 2021 | 2 | 2021 |
| A novel time-domain in-memory computing unit using STT-MRAM A Saha, S Alla, VK Joshi Microelectronic Engineering, 112128, 2023 | 1 | 2023 |