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Kaushik Roy
Kaushik Roy
Professor of Electrical and Computer Engineering, Purdue University
在 purdue.edu 的电子邮件经过验证 - 首页
标题
引用次数
引用次数
年份
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
K Roy, S Mukhopadhyay, H Mahmoodi-Meimand
Proceedings of the IEEE 91 (2), 305-327, 2003
32122003
Towards spike-based machine intelligence with neuromorphic computing
K Roy, A Jaiswal, P Panda
Nature 575 (7784), 607-617, 2019
17702019
Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates
Q Cao, H Kim, N Pimparkar, JP Kulkarni, C Wang, M Shim, K Roy, ...
Nature 454 (7203), 495-500, 2008
14072008
Going deeper in spiking neural networks: VGG and residual architectures
A Sengupta, Y Ye, R Wang, C Liu, K Roy
Frontiers in neuroscience 13, 95, 2019
12382019
Gated-Vdd a circuit technique to reduce leakage in deep-submicron cache memories
M Powell, SH Yang, B Falsafi, K Roy, TN Vijaykumar
Proceedings of the 2000 international symposium on Low power electronics and …, 2000
11542000
Low-power CMOS VLSI circuit design
K Roy, SC Prasad
John Wiley & Sons, 2009
9862009
Low-power digital signal processing using approximate adders
V Gupta, D Mohapatra, A Raghunathan, K Roy
IEEE transactions on computer-aided design of integrated circuits and …, 2012
9822012
Analysis and characterization of inherent application resilience for approximate computing
VK Chippa, ST Chakradhar, K Roy, A Raghunathan
Proceedings of the 50th Annual Design Automation Conference, 1-9, 2013
6742013
A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS
IJ Chang, JJ Kim, SP Park, K Roy
IEEE Journal of Solid-State Circuits 44 (2), 650-658, 2009
6742009
IMPACT: IMPrecise adders for low-power approximate computing
V Gupta, D Mohapatra, SP Park, A Raghunathan, K Roy
IEEE/ACM International Symposium on Low Power Electronics and Design, 409-414, 2011
6202011
A 160 mV robust Schmitt trigger based subthreshold SRAM
JP Kulkarni, K Kim, K Roy
IEEE Journal of Solid-State Circuits 42 (10), 2303-2313, 2007
6152007
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
S Mukhopadhyay, H Mahmoodi, K Roy
IEEE transactions on computer-aided design of integrated circuits and …, 2005
6102005
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks
Z Chen, M Johnson, L Wei, K Roy
Proceedings of the 1998 international symposium on Low power electronics and …, 1998
5191998
PUMA: A programmable ultra-efficient memristor-based accelerator for machine learning inference
A Ankit, IE Hajj, SR Chalamalasetti, G Ndu, M Foltin, RS Williams, ...
Proceedings of the twenty-fourth international conference on architectural …, 2019
4972019
Enabling spike-based backpropagation for training deep neural network architectures
C Lee, SS Sarwar, P Panda, G Srinivasan, K Roy
Frontiers in neuroscience 14, 497482, 2020
4692020
Roadmap of spin–orbit torques
Q Shao, P Li, L Liu, H Yang, S Fukami, A Razavi, H Wu, K Wang, ...
IEEE transactions on magnetics 57 (7), 1-39, 2021
4312021
Design and optimization of dual-threshold circuits for low-voltage low-power applications
L Wei, Z Chen, K Roy, MC Johnson, Y Ye, VK De
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (1), 16-24, 1999
4141999
SALSA: Systematic logic synthesis of approximate circuits
S Venkataramani, A Sabne, V Kozhikkottu, K Roy, A Raghunathan
Proceedings of the 49th Annual Design Automation Conference, 796-801, 2012
4112012
Computing in memory with spin-transfer torque magnetic RAM
S Jain, A Ranjan, K Roy, A Raghunathan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 470-483, 2017
4012017
Rmp-snn: Residual membrane potential neuron for enabling deeper high-accuracy and low-latency spiking neural network
B Han, G Srinivasan, K Roy
Proceedings of the IEEE/CVF conference on computer vision and pattern …, 2020
3952020
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