| Computing in memory with spin-transfer torque magnetic ram S Jain, A Ranjan, K Roy, A Raghunathan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 470-483, 2017 | 401 | 2017 |
| AxNN: Energy-efficient neuromorphic systems using approximate computing S Venkataramani, A Ranjan, K Roy, A Raghunathan Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 339 | 2014 |
| Scaledeep: A scalable compute architecture for learning and evaluating deep networks S Venkataramani, A Ranjan, S Banerjee, D Das, S Avancha, ... Proceedings of the 44th Annual International Symposium on Computer …, 2017 | 283 | 2017 |
| ASLAN: Synthesis of approximate sequential circuits A Ranjan, A Raha, S Venkataramani, K Roy, A Raghunathan 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 163 | 2014 |
| Approximate storage for energy efficient spintronic memories A Ranjan, S Venkataramani, X Fong, K Roy, A Raghunathan Proceedings of the 52nd Annual Design Automation Conference, 195, 2015 | 117 | 2015 |
| RaPiD: AI Accelerator for Ultra-low Precision Training and Inference S Venkataramani, V Srinivasan, W Wang, S Sen, J Zhang, A Agrawal, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 92 | 2021 |
| Apparatuses, methods, and systems for neural networks S Venkataramani, D Das, A Ranjan, S Banerjee, S Avancha, ... US Patent App. 16/317,497, 2019 | 59 | 2019 |
| STAxCache: An approximate, energy efficient STT-MRAM cache A Ranjan, S Venkataramani, Z Pajouhi, R Venkatesan, K Roy, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 52 | 2017 |
| X-MANN: A crossbar based architecture for memory augmented neural networks A Ranjan, S Jain, JR Stevens, D Das, B Kaul, A Raghunathan Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 47 | 2019 |
| Approximate memory compression for energy-efficiency A Ranjan, A Raha, V Raghunathan, A Raghunathan 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 38 | 2017 |
| System and method for in-memory computing S Jain, A Ranjan, K Roy, A Raghunathan US Patent 10,073,733, 2018 | 33 | 2018 |
| Manna: An Accelerator for Memory-Augmented Neural Networks JR Stevens, A Ranjan, D Das, B Kaul, A Raghunathan Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 31 | 2019 |
| AxBA: An approximate bus architecture framework JR Stevens, A Ranjan, A Raghunathan 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 31 | 2018 |
| Approximate Memory Compression A Ranjan, A Raha, V Raghunathan, A Raghunathan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (4), 980-991, 2020 | 25 | 2020 |
| Dyrectape: a dynamically reconfigurable cache using domain wall memory tapes A Ranjan, SG Ramasubramanian, R Venkatesan, V Pai, K Roy, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 181-186, 2015 | 21 | 2015 |
| System and method for in-memory computing S Jain, A Ranjan, K Roy, A Raghunathan US Patent App. 10/073,733, 2018 | 16* | 2018 |
| Cache Memory Design With Magnetic Skyrmions in a Long Nanotrack MC Chen, A Ranjan, A Raghunathan, K Roy IEEE Transactions on Magnetics 55 (8), 1-9, 2019 | 10 | 2019 |
| Apparatuses, methods, and systems for access synchronization in a shared memory S Venkataramani, D Das, S Avancha, A Ranjan, S Banerjee, K Bharat, ... US Patent 11,106,464, 2021 | 6 | 2021 |
| Emerging neural workloads and their impact on hardware D Brooks, MM Frank, T Gokmen, U Gupta, XS Hu, S Jain, AF Laguna, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 6 | 2020 |
| Approximate cache memory A Ranjan, S Venkataramani, Z Pajouhi, R Venkatesan, K Roy, ... US Patent 10,255,186, 2019 | 5 | 2019 |
Anand RaghunathanSilicon Valley Chair Professor of Electrical and Computer Engineering, Purdue University在 purdue.edu 的电子邮件经过验证