| Leakage current: Moore's law meets static power NS Kim, T Austin, D Baauw, T Mudge, K Flautner, JS Hu, MJ Irwin, ... computer 36 (12), 68-75, 2003 | 1806 | 2003 |
| The design and use of simplepower: a cycle-accurate energy estimation tool W Ye, N Vijaykrishnan, M Kandemir, MJ Irwin Proceedings of the 37th Annual Design Automation Conference, 340-345, 2000 | 684 | 2000 |
| Design and management of 3D chip multiprocessors using network-in-memory F Li, C Nicopoulos, T Richardson, Y Xie, V Narayanan, M Kandemir ACM SIGARCH Computer Architecture News 34 (2), 130-141, 2006 | 552 | 2006 |
| Analysis of error recovery schemes for networks on chips S Murali, T Theocharides, N Vijaykrishnan, MJ Irwin, L Benini, ... IEEE Design & Test of Computers 22 (5), 434-442, 2005 | 444 | 2005 |
| ViChaR: A dynamic virtual channel regulator for network-on-chip routers CA Nicopoulos, D Park, J Kim, N Vijaykrishnan, MS Yousif, CR Das 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006 | 434 | 2006 |
| Dynamic management of scratch-pad memory space M Kandemir, J Ramanujam, J Irwin, N Vijaykrishnan, I Kadayif, A Parikh Proceedings of the 38th annual Design Automation Conference, 690-695, 2001 | 402 | 2001 |
| A novel dimensionally-decomposed router for on-chip communication in 3D architectures J Kim, C Nicopoulos, D Park, R Das, Y Xie, V Narayanan, MS Yousif, ... Proceedings of the 34th annual international symposium on Computer …, 2007 | 365 | 2007 |
| A low latency router supporting adaptivity for on-chip interconnects J Kim, D Park, T Theocharides, N Vijaykrishnan, CR Das Proceedings of the 42nd annual Design Automation Conference, 559-564, 2005 | 361 | 2005 |
| Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs A Jog, AK Mishra, C Xu, Y Xie, V Narayanan, R Iyer, CR Das Proceedings of the 49th Annual Design Automation Conference, 243-252, 2012 | 360 | 2012 |
| Energy-driven integrated hardware-software optimizations using SimplePower N Vijaykrishnan, M Kandemir, MJ Irwin, HS Kim, W Ye ACM SIGARCH Computer Architecture News 28 (2), 95-106, 2000 | 350 | 2000 |
| Exploring fault-tolerant network-on-chip architectures D Park, C Nicopoulos, J Kim, N Vijaykrishnan, CR Das International Conference on Dependable Systems and Networks (DSN'06), 93-104, 2006 | 322 | 2006 |
| Fault tolerant algorithms for network-on-chip interconnect M Pirretti, GM Link, RR Brooks, N Vijaykrishnan, M Kandemir, MJ Irwin IEEE computer society annual symposium on VLSI, 46-51, 2004 | 309 | 2004 |
| A gracefully degrading and energy-efficient modular router architecture for on-chip networks J Kim, C Nicopoulos, D Park, V Narayanan, MS Yousif, CR Das ACM SIGARCH Computer Architecture News 34 (2), 4-15, 2006 | 306 | 2006 |
| MIRA: A multi-layered on-chip interconnect router architecture D Park, S Eachempati, R Das, AK Mishra, Y Xie, N Vijaykrishnan, CR Das ACM SIGARCH Computer Architecture News 36 (3), 251-261, 2008 | 302 | 2008 |
| Architecture exploration for ambient energy harvesting nonvolatile processors K Ma, Y Zheng, S Li, K Swaminathan, X Li, Y Liu, J Sampson, Y Xie, ... 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 301 | 2015 |
| Using complete machine simulation for software power estimation: The softwatt approach S Gurumurthi, A Sivasubramaniam, MJ Irwin, N Vijaykrishnan, ... Proceedings Eighth International Symposium on High Performance Computer …, 2002 | 297 | 2002 |
| Reducing leakage energy in FPGAs using region-constrained placement A Gayasen, Y Tsai, N Vijaykrishnan, M Kandemir, MJ Irwin, T Tuan Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field …, 2004 | 286 | 2004 |
| Temperature-Dependent–Characteristics of a VerticalTunnel FET S Mookerjea, D Mohata, T Mayer, V Narayanan, S Datta IEEE Electron Device Letters 31 (6), 564-566, 2010 | 259 | 2010 |
| On enhanced Miller capacitance effect in interband tunnel transistors S Mookerjea, R Krishnan, S Datta, V Narayanan IEEE Electron Device Letters 30 (10), 1102-1104, 2009 | 258 | 2009 |
| Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs R Das, S Eachempati, AK Mishra, V Narayanan, CR Das 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 256 | 2009 |
Mary Jane (Janie) IrwinEmerita Evan Pugh University Professor, CSE, Penn State University在 cse.psu.edu 的电子邮件经过验证
