| New dual material double gate junctionless tunnel FET: Subthreshold modeling and simulation GL Priya, NB Balamurugan AEU-International Journal of Electronics and Communications 99, 130-138, 2019 | 62 | 2019 |
| Analytical approach of a nanoscale triple-material surrounding gate (TMSG) MOSFETs for reduced short-channel effects PS Dhanaselvam, NB Balamurugan Microelectronics Journal 44 (5), 400-404, 2013 | 54 | 2013 |
| Analytical modelling and simulation of single-gate SOI TFET for low-power applications TS Arun Samuel, NB Balamurugan, S Bhuvaneswari, D Sharmila, ... International Journal of Electronics 101 (6), 779-788, 2014 | 52 | 2014 |
| 2D analytical modeling and simulation of dual material DG MOSFET for biosensing application B Buvaneswari, NB Balamurugan AEU-International Journal of Electronics and Communications 99, 193-200, 2019 | 45 | 2019 |
| Analytical modeling of InSb/AlInSb heterostructure dual gate high electron mobility transistors TV Kumar, NB Balamurugan AEU-International Journal of Electronics and Communications 94, 19-25, 2018 | 40 | 2018 |
| Influence of threshold voltage performance analysis on dual halo gate stacked triple material dual gate TFET for ultra low power applications M Venkatesh, NB Balamurugan Silicon 13, 275-287, 2021 | 35 | 2021 |
| New subthreshold performance analysis of germanium based dual halo gate stacked triple material surrounding gate tunnel field effect transistor M Venkatesh, NB Balamurugan Superlattices and Microstructures 130, 485-498, 2019 | 33 | 2019 |
| Three-dimensional analytical modeling for small-geometry AlInSb/AlSb/InSb double-gate high-electron-mobility transistors (DG-HEMTs) T Venish Kumar, NB Balamurugan Journal of Computational Electronics 19, 1107-1115, 2020 | 31 | 2020 |
| Analytical threshold voltage modeling of surrounding gate silicon nanowire transistors with different geometries MK Pandian, NB Balamurugan Journal of Electrical Engineering and Technology 9 (6), 2079-2088, 2014 | 30 | 2014 |
| Analytical modeling and simulation of dual material gate tunnel field effect transistors TS Samuel, NB Balamurugan, S Sibitha, R Saranya, D Vanisri Journal of Electrical Engineering and Technology 8 (6), 1481-1486, 2013 | 28 | 2013 |
| An analytical modeling and simulation of dual material double gate tunnel field effect transistor for low power applications TS Arun Samuel, NB Balamurugan Journal of electrical engineering and technology 9 (1), 247-253, 2014 | 25 | 2014 |
| A 2D Transconductance and Sub-threshold behavior model for triple material surrounding gate (TMSG) MOSFETs PS Dhanaselvam, NB Balamurugan, VN Ramakrishnan Microelectronics Journal 44 (12), 1159-1164, 2013 | 25 | 2013 |
| 2D Transconductance to Drain Current Ratio Modeling of Dual Material Surrounding Gate Nanoscale SOl MOSFETs NB Balamurugan, K Sankaranarayanan, MF John JSTS: Journal of Semiconductor Technology and Science 9 (2), 110-116, 2009 | 24 | 2009 |
| Influence of germanium source dual halo dual dielectric triple material surrounding gate tunnel FET for improved analog/RF performance M Venkatesh, M Suguna, NB Balamurugan Silicon 12, 2869-2877, 2020 | 23 | 2020 |
| Subthreshold performance analysis of germanium source dual halo dual dielectric triple material surrounding gate tunnel field effect transistor for ultra low power applications M Venkatesh, M Suguna, NB Balamurugan Journal of Electronic Materials 48, 6724-6734, 2019 | 23 | 2019 |
| The improved RF/stability and linearity performance of the ultrathin-body Gaussian-doped junctionless FinFET S Manikandan, NB Balamurugan Journal of Computational Electronics 19 (2), 613-621, 2020 | 22 | 2020 |
| Triple material surrounding gate (TMSG) nanoscale tunnel FET-analytical modeling and simulation P Vanitha, NB Balamurugan, GL Priya JSTS: Journal of Semiconductor Technology and Science 15 (6), 585-593, 2015 | 22 | 2015 |
| New analytical model for nanoscale tri-gate SOI MOSFETs including quantum effects P Vimala, NB Balamurugan IEEE Journal of the Electron Devices Society 2 (1), 1-7, 2014 | 22 | 2014 |
| Triple metal surrounding gate junctionless tunnel FET based 6T SRAM design for low leakage memory system GL Priya, M Venkatesh, NB Balamurugan, TSA Samuel Silicon 13, 1691-1702, 2021 | 21 | 2021 |
| Analytical model of double gate stacked oxide junctionless transistor considering source/drain depletion effects for CMOS low power applications S Manikandan, NB Balamurugan, D Nirmal Silicon 12, 2053-2063, 2020 | 20 | 2020 |
Dr LAKSHMI PRIYA GAssociate Professor, VIT University, Chennai.在 vit.ac.in 的电子邮件经过验证