| Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability J Madan, R Chaujar IEEE Transactions on Device and Materials Reliability 16 (2), 227-234, 2016 | 212 | 2016 |
| Numerical Simulation of N+Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature J Madan, R Chaujar IEEE Transactions on Electron Devices 64 (4), 1482-1488, 2017 | 102 | 2017 |
| Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor SP Kumar, A Agrawal, R Chaujar, RS Gupta, M Gupta Microelectronics Reliability 51 (3), 587-596, 2011 | 101 | 2011 |
| Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance J Madan, R Chaujar Superlattices and Microstructures 102, 17-26, 2017 | 80 | 2017 |
| Numerical simulations: Toward the design of 27.6% efficient four-terminal semi-transparent perovskite/SiC passivated rear contact silicon tandem solar cell R Pandey, R Chaujar Superlattices and Microstructures 100, 656-666, 2016 | 78 | 2016 |
| TCAD RF performance investigation of transparent gate recessed channel MOSFET A Kumar, N Gupta, R Chaujar Microelectronics Journal 49, 36-42, 2016 | 61 | 2016 |
| Optimization of high-k and gate metal workfunction for improved analog and intermodulation performance of Gate Stack (GS)-GEWE-SiNW MOSFET N Gupta, R Chaujar Superlattices and Microstructures 97, 630-641, 2016 | 57 | 2016 |
| Analog and RF performance evaluation of junctionless accumulation mode (JAM) gate stack gate all around (GS-GAA) FinFET B Kumar, R Chaujar Silicon 13, 919-927, 2021 | 56 | 2021 |
| Temperature associated reliability issues of heterogeneous gate dielectric—gate all around—tunnel FET J Madan, R Chaujar IEEE Transactions on nanotechnology 17 (1), 41-48, 2017 | 56 | 2017 |
| Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced ON state behavior J Madan, R Chaujar Applied Physics A 122, 1-9, 2016 | 56 | 2016 |
| Numerical simulations: Toward the design of 18.6% efficient and stable perovskite solar cell using reduced cerium oxide based ETL R Pandey, AP Saini, R Chaujar Vacuum 159, 173-181, 2019 | 55 | 2019 |
| Reliability Issues of In2O5Sn Gate Electrode Recessed Channel MOSFET: Impact of Interface Trap Charges and Temperature A Kumar, MM Tripathi, R Chaujar IEEE Transactions on Electron Devices 65 (3), 860-866, 2018 | 54 | 2018 |
| Analytical modeling and simulation of subthreshold behavior in nanoscale dual material gate AlGaN/GaN HEMT SP Kumar, A Agrawal, R Chaujar, M Gupta, RS Gupta Superlattices and Microstructures 44 (1), 37-53, 2008 | 53 | 2008 |
| Toward the design of monolithic 23.1% efficient hysteresis and moisture free perovskite/c-Si HJ tandem solar cell: a numerical simulation study R Pandey, A Singla, J Madan, R Sharma, R Chaujar Journal of Micromechanics and Microengineering 29 (6), 064001, 2019 | 50 | 2019 |
| Palladium gate all around-hetero dielectric-tunnel FET based highly sensitive hydrogen gas sensor J Madan, R Chaujar Superlattices and Microstructures 100, 401-408, 2016 | 48 | 2016 |
| Comprehensive analysis of sub-20 nm black phosphorus based junctionless-recessed channel MOSFET for analog/RF applications A Kumar, MM Tripathi, R Chaujar Superlattices and Microstructures 116, 171-180, 2018 | 46 | 2018 |
| Analysis of novel transparent gate recessed channel (TGRC) MOSFET for improved analog behaviour A Kumar, N Gupta, R Chaujar Microsystem technologies 22, 2665-2671, 2016 | 46 | 2016 |
| Source/gate material-engineered double gate TFET for improved RF and linearity performance: a numerical simulation S Shekhar, J Madan, R Chaujar Applied Physics A 124 (11), 739, 2018 | 45 | 2018 |
| Investigation of parasitic capacitances of In2O5Sn gate electrode recessed channel MOSFET for ULSI switching applications A Kumar, MM Tripathi, R Chaujar Microsystem Technologies 23, 5867-5874, 2017 | 45 | 2017 |
| Performance evaluation of linearity and intermodulation distortion of nanoscale GaN-SOI FinFET for RFIC design A Kumar, N Gupta, SK Tripathi, MM Tripathi, R Chaujar AEU-International Journal of Electronics and Communications 115, 153052, 2020 | 43 | 2020 |
Dr. Ajay Kumar, SMIEEEJaypee Institute of Information Technology, Noida在 jiit.ac.in 的电子邮件经过验证
