| Semiconductor device having MIS field effect transistors or three-dimensional structure S Inaba, K Ohuchi US Patent 6,525,403, 2003 | 410 | 2003 |
| Insulated-gate transistor having narrow-bandgap-source M Yoshimi, S Inaba, A Murakoshi, M Terauchi, N Shigyo, Y Matsushita, ... US Patent 5,698,869, 1997 | 322 | 1997 |
| High-performance FinFET with dopant-segregated Schottky source/drain A Kaneko, A Yagishita, K Yahashi, T Kubota, M Omura, K Matsuo, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 294 | 2006 |
| Semiconductor device including n-type and p-type FinFET's constituting an inverter structure S Inaba US Patent 7,994,583, 2011 | 230 | 2011 |
| Semiconductor device and method of fabricating the same S Inaba US Patent App. 11/723,928, 2007 | 210 | 2007 |
| Semiconductor device S Inaba US Patent 8,368,148, 2013 | 174 | 2013 |
| Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length K Okano, T Izumida, H Kawasaki, A Kaneko, A Yagishita, T Kanemura, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 140 | 2005 |
| Semiconductor device and method of manufacturing semiconductor device A Hokazono, S Inaba US Patent 7,750,381, 2010 | 130 | 2010 |
| Semiconductor device using SOI structure having a triple-well region S Inaba US Patent 7,259,428, 2007 | 123 | 2007 |
| Semiconductor device and method of fabricating the same S Inaba, T Morooka US Patent 7,449,733, 2008 | 116 | 2008 |
| Steep channel & Halo profiles utilizing boron-diffusion-barrier layers (Si: C) for 32 nm node and beyond A Hokazono, H Itokawa, N Kusunoki, I Mizushima, S Inaba, S Kawanaka, ... 2008 Symposium on VLSI Technology, 112-113, 2008 | 113 | 2008 |
| Steep channel profiles in n/pMOS controlled by boron-doped Si: C layers for continual bulk-CMOS scaling A Hokazono, H Itokawa, I Mizushima, S Kawanaka, S Inaba, Y Toyoshima 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 109 | 2009 |
| Semiconductor wafer, semiconductor device and method of fabricating the same S Inaba US Patent 8,039,843, 2011 | 103 | 2011 |
| Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension A Kaneko, A Yagishita, K Yahashi, T Kubota, M Omura, K Matsuo, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 94 | 2005 |
| Embedded bulk FinFET SRAM cell technology with planar FET peripheral circuit for hp32 nm node and beyond H Kawasaki, K Okano, A Kaneko, A Yagishita, T Izumida, T Kanemura, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 70-71, 2006 | 80 | 2006 |
| High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide S Inaba, K Okano, S Matsuda, M Fujiwara, A Hokazono, K Adachi, ... IEEE Transactions on Electron devices 49 (12), 2263-2270, 2002 | 76 | 2002 |
| Analyses of 5σ Vthfluctuation in 65nm-MOSFETs using takeuchi plot T Tsunomura, A Nishida, F Yano, AT Putra, K Takeuchi, S Inaba, ... 2008 Symposium on VLSI Technology, 156-157, 2008 | 74 | 2008 |
| Semiconductor device S Inaba US Patent App. 12/139,762, 2008 | 70 | 2008 |
| High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE S Inaba, K Okano, S Matsuda, M Fujiwara, A Hokazono, K Adachi, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 52 | 2001 |
| Semiconductor device S Inaba US Patent 8,169,009, 2012 | 45 | 2012 |
