| ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist RS Rajarathnam, Y Lin, Y Jin, DZ Pan 2020 IEEE International Symposium on Hardware Oriented Security and Trust …, 2020 | 39 | 2020 |
| DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit RS Rajarathnam, MB Alawieh, Z Jiang, M Iyer, DZ Pan 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 300-306, 2022 | 21 | 2022 |
| VLSI implementation of Piecewise Approximated antilogarithmic converter RR Selina 2013 International Conference on Communication and Signal Processing, 763-766, 2013 | 11 | 2013 |
| DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs RS Rajarathnam, Z Jiang, MA Iyer, DZ Pan Proceedings of the 2023 International Symposium on Physical Design, 175-184, 2023 | 8 | 2023 |
| ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection R Zhang, RS Rajarathnam, DZ Pan, F Koushanfar arXiv preprint arXiv:2404.18407, 2024 | 2 | 2024 |
| Automated Physical Design Watermarking Leveraging Graph Neural Networks R Zhang, RS Rajarathnam, DZ Pan, F Koushanfar arXiv preprint arXiv:2407.20544, 2024 | 1 | 2024 |
| A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs Z Xiong, RS Rajarathnam, DZ Pan 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom …, 2024 | 1 | 2024 |
| DREAMPlaceFPGA-MP: An Open-Source GPU-Accelerated Macro Placer for Modern FPGAs with Cascade Shapes and Region Constraints Z Xiong, RS Rajarathnam, Z Jiang, H Zhu, DZ Pan arXiv preprint arXiv:2311.08582, 2023 | 1 | 2023 |
| Better Together: Combining Analytical and Annealing Methods for FPGA Placement RS Rajarathnam, K Thurmer, V Betz, MA Iyer, DZ Pan 2024 34th International Conference on Field-Programmable Logic and …, 2024 | | 2024 |
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at Austin在 ece.utexas.edu 的电子邮件经过验证