| Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges EP Gusev, V Narayanan, MM Frank IBM Journal of Research and Development 50 (4.5), 387-410, 2006 | 393 | 2006 |
| Switching of ferroelectric polarization in epitaxial BaTiO3 films on silicon without a conducting bottom electrode C Dubourdieu, J Bruley, TM Arruda, A Posadas, J Jordan-Sweet, ... Nature nanotechnology 8 (10), 748, 2013 | 300 | 2013 |
| A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates S Zafar, Y Kim, V Narayanan, C Cabral, V Paruchuri, B Doris, J Stathis, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 23-25, 2006 | 293 | 2006 |
| High-/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length MH Khater, Z Zhang, J Cai, C Lavoie, C D'Emic, Q Yang, B Yang, ... IEEE Electron Device Letters 31 (4), 275-277, 2010 | 265 | 2010 |
| Oxygen vacancies in high dielectric constant oxide-semiconductor films S Guha, V Narayanan Physical review letters 98 (19), 196101, 2007 | 256 | 2007 |
| Ultimate scaling of high-κ gate dielectrics: Higher-κ or interfacial layer scavenging? T Ando Materials 5 (3), 478-500, 2012 | 213 | 2012 |
| A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference M Le Gallo, R Khaddam-Aljameh, M Stanisavljevic, A Vasilopoulos, ... Nature Electronics 6 (9), 680-693, 2023 | 157 | 2023 |
| HERMES Core–A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing R Khaddam-Aljameh, M Stanisavljevic, JF Mas, G Karunaratne, ... 2021 Symposium on VLSI Circuits, 1-2, 2021 | 141 | 2021 |
| Comparative study of GaN and AlN nucleation layers and their role in growth of GaN on sapphire by metalorganic chemical vapor deposition K Lorenz, M Gonsalves, W Kim, V Narayanan, S Mahajan Applied Physics Letters 77 (21), 3391-3393, 2000 | 136 | 2000 |
| Origins of threading dislocations in GaN epitaxial layers grown on sapphire by metalorganic chemical vapor deposition V Narayanan, K Lorenz, W Kim, S Mahajan Applied Physics Letters 78 (11), 1544-1546, 2001 | 133 | 2001 |
| A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process X Chen, S Samavedam, V Narayanan, K Stein, C Hobbs, C Baiocco, W Li, ... 2008 symposium on vlsi technology, 88-89, 2008 | 131 | 2008 |
| A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ... 2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011 | 129 | 2011 |
| Fundamental aspects of HfO2-based high-k metal gate stack reliability and implications on tinv-scaling E Cartier, A Kerber, T Ando, MM Frank, K Choi, S Krishnan, B Linder, ... 2011 International Electron Devices Meeting, 18.4. 1-18.4. 4, 2011 | 124 | 2011 |
| Signal and noise extraction from analog memory elements for neuromorphic computing N Gong, T Idé, S Kim, I Boybat, A Sebastian, V Narayanan, T Ando Nature communications 9 (1), 2102, 2018 | 123 | 2018 |
| Examination of flatband and threshold voltage tuning of HfO2∕ TiN field effect transistors by dielectric cap layers S Guha, VK Paruchuri, M Copel, V Narayanan, YY Wang, PE Batson, ... Applied physics letters 90 (9), 2007 | 123 | 2007 |
| High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, ... 2007 IEEE symposium on VLSI technology, 194-195, 2007 | 122 | 2007 |
| Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and Vt-tuning dipoles with gate … T Ando, MM Frank, K Choi, C Choi, J Bruley, M Hopstaken, M Copel, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 115 | 2009 |
| A flexible and fast PyTorch toolkit for simulating training and inference on analog crossbar arrays MJ Rasch, D Moreda, T Gokmen, M Le Gallo, F Carta, C Goldberg, ... 2021 IEEE 3rd international conference on artificial intelligence circuits …, 2021 | 112 | 2021 |
| High-k/metal gate innovations enabling continued CMOS scaling MM Frank 2011 Proceedings of the European Solid-State Device Research Conference …, 2011 | 112 | 2011 |
| An analog-AI chip for energy-efficient speech recognition and transcription S Ambrogio, P Narayanan, A Okazaki, A Fasoli, C Mackin, K Hosokawa, ... Nature 620 (7975), 768-775, 2023 | 110 | 2023 |
Takashi AndoIBM T. J. Watson Research Center在 us.ibm.com 的電子郵件地址已通過驗證
