Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs

C Bernardeschi, L Cassano… - … on Defect and Fault …, 2012 - ieeexplore.ieee.org
SRAM-based FPGAs are more and more relevant in a growing number of applications,
ranging from the automotive to the aerospace ones. Designers of safety-critical applications …

ASSESS: A simulator of soft errors in the configuration memory of SRAM-based FPGAs

C Bernardeschi, L Cassano… - … on Computer-Aided …, 2014 - ieeexplore.ieee.org
In this paper a simulator of soft errors (SEUs) in the configuration memory of SRAM-based
FPGAs is presented. The simulator, named ASSESS, adopts fault models for SEUs affecting …

GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs

C Bernardeschi, L Cassano, MGCA Cimino… - Journal of Systems …, 2013 - Elsevier
Testing of FPGAs is gaining more and more interest because of the application of FPGA
devices in many safety-critical systems. We propose GABES, a tool for the generation of test …

[PDF][PDF] Formal verification in the loop to enhance verification of safety-critical cyber-physical systems

C Bernardeschi, A Domenici, S Saponara - … Communications of the …, 2019 - eceasst.org
Formal verification may play a central role in the development of safe controllers, such as
those found in electric drives or (semi-) autonomous vehicles, whose complexity arises from …

[PDF][PDF] Application of a genetic algorithm for testing SEUs in SRAM-FPGA Systems

C Bernardeschi, L Cassano, M Cimino… - Proceedings of the …, 2012 - docenti.ing.unipi.it
Testing of FPGAs is gaining more and more interest because of the employment of FPGA
devices in many safety-critical application fields. We propose a prototype of a tool for the …

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

L Cassano - 2014 International Test Conference, 2014 - ieeexplore.ieee.org
In the Ph. D. thesis1 from which this summary has been extracted the author proposed a
framework of methodologies for the analysis and test of the effects of Single Event Upsets …

[PDF][PDF] Interactive Workshop on the Industrial Application of Verification and Testing ETAPS 2020 Workshop (InterAVT 2020)

A Mjeda, G Botterweck - Electronic Communications of the …, 2020 - researchrepository.ul.ie
When designing and analysing autonomous systems and their environment it is necessary
to consider uncertainty and multiple potential states (of the system and its environment). In …

[PDF][PDF] Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs.

L Cassano - 2013 - core.ac.uk
SRAM-based FPGAs are increasingly relevant in a growing number of safety-critical
application fields, ranging from automotive to aerospace. These application fields are …

Towards Stochastic FMI Co-simulations: Implementation of an FMU for a Stochastic Activity Networks Simulator

C Bernardeschi, A Domenici, M Palmieri - Federation of International …, 2018 - Springer
The advantage of co-simulation with respect to traditional single-paradigm simulation lies
mainly in the modeling flexibility it affords in composing large models out of submodels …

Spolehlivé architektury FPGA

P Jan - 2019 - search.proquest.com
The digital device known as Field Programmable Gate Array (FPGA) combines a reasonable
computational power together with an ability to be reprogrammed. Its functionality (whole or …