Non-volatile memory (NVM) opens up new opportunities to resolve scaling restrictions of
main memory, yet it is still hindered by the write disturbance (WD) problem. The WD problem …

This paper introduces VeriGOOD-ML, an automated methodology for generating Verilog
with no human in the loop, starting from a high-level description of a machine learning (ML) …

When a coarse-grained reconfigurable array (CGRA) architecture shifts toward cross-
domain acceleration, control flow and memory accesses often degrade the processing …

ML accelerators have largely focused on building general platforms for deep neural
networks (DNNs), but less so on shallow machine learning (SML) algorithms. This paper …

Recently, there has been an extensive research effort in building efficient large language
model (LLM) inference serving systems. These efforts not only include innovations in the …

Edge systems are required to autonomously make real-time decisions based on large
quantities of input data under strict power, performance, area, and other constraints. Meeting …

Dataflow architectures can achieve much better performance and higher efficiency than
general-purpose core, approaching the performance of a specialized design while retaining …

As emerging applications raise ever-boosting and varying computational demand, the
reconfigurable accelerator is becoming prevalent due to balanced performance, efficiency …

In this paper, we present a novel technique to search for hardware architectures of
accelerators optimized for end-to-end training of deep neural networks (DNNs). Our …

Application-specific instruction-set processors (ASIP) has been widely used to speedup
specific applications based on general-purpose processor (CPU) ISA-extension and …