[KSIĄŻKA][B] Low power methodology manual: for system-on-chip design
D Flynn, R Aitken, A Gibbons, K Shi - 2007 - books.google.com
“Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs-
a well-planned methodology is needed. Following in the footsteps of the successful Reuse …
a well-planned methodology is needed. Following in the footsteps of the successful Reuse …
Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By
adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error …
adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error …
[PDF][PDF] Delay-power performance comparison of multipliers in VLSI circuit design
S Vaidya, D Dandekar - International Journal of Computer Networks …, 2010 - academia.edu
A typical processor central processing unit devotes a considerable amount of processing
time in performing arithmetic operations, particularly multiplication operations. Multiplication …
time in performing arithmetic operations, particularly multiplication operations. Multiplication …
[HTML][HTML] A novel approach for design energy efficient inexact reverse carry select adders for IoT applications
Low cost, low form factor and highly energy efficient VLSI design is the key for the success of
internet of things (IoT) paradigm. Approximate computing is one of the major techniques …
internet of things (IoT) paradigm. Approximate computing is one of the major techniques …
[KSIĄŻKA][B] Low-power high-level synthesis for nanoscale CMOS circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for
analysis, characterization, estimation, and optimization of the various forms of power …
analysis, characterization, estimation, and optimization of the various forms of power …
Benchmarking of Standard-Cell Based Memories in the Sub- Domain in 65-nm CMOS Technology
In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-
custom sub-V T SRAM macros for ultra-low-power systems requiring small memory blocks …
custom sub-V T SRAM macros for ultra-low-power systems requiring small memory blocks …
Towards generic low-power area-efficient standard cell based memory architectures
Digital IC designers often use SRAM macrocells to implement on-chip memory functionality.
In this paper we argue that in several situations, standard cell based memories (SCMs) can …
In this paper we argue that in several situations, standard cell based memories (SCMs) can …
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells
Leakage estimation is an important step in nano-scale technology digital design flows. While
reliable data exist on leakage trends with bulk CMOS technology scaling in stand-alone …
reliable data exist on leakage trends with bulk CMOS technology scaling in stand-alone …
Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier
N Yin, W Pan, Y Yu, C Tang, Z Yu - Electronics, 2023 - mdpi.com
With the rapid development of information technology, the demand for high-speed and low-
power technology for digital signal processing is increasing. Full adders and multipliers are …
power technology for digital signal processing is increasing. Full adders and multipliers are …
[KSIĄŻKA][B] Top-down digital VLSI design: from architectures to gate-level circuits and FPGAs
H Kaeslin - 2014 - books.google.com
Top-Down VLSI Design: From Architectures to Gate-Level Circuits and FPGAs represents a
unique approach to learning digital design. Developed from more than 20 years teaching …
unique approach to learning digital design. Developed from more than 20 years teaching …