Dos and don'ts of machine learning in computer security

D Arp, E Quiring, F Pendlebury, A Warnecke… - 31st USENIX Security …, 2022 - usenix.org
With the growing processing power of computing systems and the increasing availability of
massive datasets, machine learning algorithms have led to major breakthroughs in many …

The rise of website fingerprinting on Tor: Analysis on techniques and assumptions

MAIM Aminuddin, ZF Zaaba, A Samsudin, F Zaki… - Journal of Network and …, 2023 - Elsevier
Tor is one of the most popular anonymity networks that allows Internet users to hide their
browsing activity. Hiding browsing activity is essential for Internet users to increase their …

Timing Side-Channel Attacks and Countermeasures in CPU Microarchitectures

J Zhang, C Chen, J Cui, K Li - ACM Computing Surveys, 2024 - dl.acm.org
Microarchitectural vulnerabilities, such as Meltdown and Spectre, exploit subtle
microarchitecture state to steal the user's secret data and even compromise the operating …

Cache telepathy: Leveraging shared resource attacks to learn {DNN} architectures

M Yan, CW Fletcher, J Torrellas - 29th USENIX Security Symposium …, 2020 - usenix.org
Deep Neural Networks (DNNs) are fast becoming ubiquitous for their ability to attain good
accuracy in various machine learning tasks. A DNN's architecture (ie, its hyperparameters) …

Mi6: Secure enclaves in a speculative out-of-order processor

T Bourgeat, I Lebedev, A Wright, S Zhang… - Proceedings of the …, 2019 - dl.acm.org
Recent attacks have broken process isolation by exploiting microarchitectural side channels
that allow indirect access to shared microarchitectural state. Enclaves strengthen the …

Prime+ Scope: Overcoming the observer effect for high-precision cache contention attacks

A Purnal, F Turan, I Verbauwhede - Proceedings of the 2021 ACM …, 2021 - dl.acm.org
Modern processors expose software to information leakage through shared
microarchitectural state. One of the most severe leakage channels is cache contention …

{MIRAGE}: Mitigating {Conflict-Based} Cache Attacks with a Practical {Fully-Associative} Design

G Saileshwar, M Qureshi - 30th USENIX Security Symposium (USENIX …, 2021 - usenix.org
Shared caches in processors are vulnerable to conflict-based side-channel attacks, whereby
an attacker can monitor the access pattern of a victim by evicting victim cache lines using …

{HybCache}: Hybrid {Side-Channel-Resilient} caches for trusted execution environments

G Dessouky, T Frassetto, AR Sadeghi - 29th USENIX Security …, 2020 - usenix.org
Modern multi-core processors share cache resources for maximum cache utilization and
performance gains. However, this leaves the cache vulnerable to side-channel attacks …

Synchronization Storage Channels ({{{{{S2C)}}}}}: Timer-less Cache {Side-Channel} Attacks on the Apple M1 via Hardware Synchronization Instructions

J Yu, A Dutta, T Jaeger, D Kohlbrenner… - 32nd USENIX Security …, 2023 - usenix.org
Shared caches have been a prime target for mounting crossprocess/core side-channel
attacks. Fundamentally, these attacks require a mechanism to accurately observe changes …

{Prime+ Probe} 1,{JavaScript} 0: Overcoming Browser-based {Side-Channel} Defenses

A Shusterman, A Agarwal, S O'Connell… - 30th USENIX Security …, 2021 - usenix.org
Prime+Probe 1, JavaScript 0: Overcoming Browser-based Side-Channel Defenses Page 1
This paper is included in the Proceedings of the 30th USENIX Security Symposium. August …