Techniques are disclosed relating to suspending execution of a processor thread while
monitoring for a write to a specified memory location. An execution subsystem may be …

A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to
receive a single instruction multiple data (SIMD) instruction to perform an operation on …

In one embodiment, a processor can operate in multiple modes, including a direct execution
mode and an emulation execution mode. More specifically, the processor may operate in a …

An electronic device is configured to manage heat in the device using a multi level thermal
management process. When the temperature of the device reaches a level that requires the …

BACKGROUND Modern microprocessors are at the heart of most computer systems. In
general, these processors operate by receiving instructions and performing operations …

A processor of an aspect includes a decode unit to decode a thread pause instruction from a
first thread. A back-end portion of the processor is coupled with the decode unit. The back …

kkS/3 ()(201801) An apparatus includes a buffer, a sequencing circuit, and an c00c 0S00
l0L0S execution unit. The buffer may be configured to store a 52) US CI plurality of …

In one embodiment, a processor can operate in multiple modes, including a direct execution
mode and an emulation execution mode. More specifically, the processor may operate in a …

In an embodiment, a processor includes a first processor core, a second processor core, a
first Voltage regulator to provide a first voltage to the first processor core with a first active …

BACKGROUND 0002 An aspect of the present invention relates, in gen eral, to emulated
computing environments, and in particular, to facilitating processing within Such …