In computer architecture studies, simulators are crucial for design verification, reducing
research and development time and ensuring the high accuracy of verification results …

Modern computing systems employ significant heterogeneity and specialization to meet
performance targets at manageable power. However, memory latency bottlenecks remain …

In this work, we present a C ompiler-integrated, E xtensible D omain Specific System on
Chip R untime (CEDR) ecosystem to facilitate research toward addressing the challenges of …

The design space exploration of scaled-out manycores for communication-intensive
applications (eg, graph analytics and sparse linear algebra) is hampered due to either lack …

Covert channels enable information leakage between security domains that should be
isolated by observing execution differences in shared hardware. These channels can …

Graph structures are a natural representation of important and pervasive data. While graph
applications have significant parallelism, their characteristic pointer indirect loads to …

To tackle the challenges posed by Moore's Law, Chiplet technology emerges as a promising
solution. Chiplets comprising CPUs and accelerators are connected by Networks-on-Chip …

Despite their ubiquity in many important big-data applications, graph analytic kernels
continue to challenge modern memory hierarchies due to their frequent, long-latency …

As the computing landscape evolves, system designers continue to explore design
methodologies that leverage increased levels of heterogeneity to push performance within …

As Moore's Law has slowed and Dennard Scaling has ended, architects are increasingly
turning to heterogeneous parallelism and hardware-software co-design. These trends …