The number of gates on a chip is quickly growing toward and beyond the one billion mark.
Kee** all the gates running at the beat of a single or a few rationally related clocks is …

This article describes how actual trends of networks-on-chip research and known
approaches to their modeling are considered. The characteristics of analytic and high-/low …

This paper describes the System Verilog modeling language developed by Tiempo to
design asynchronous circuits. The language enables designers to model, verify and debug …

This paper presents comparison of transient fault effects in an asynchronous NoC router and
a synchronous one. The experiment is based on simulation-based fault injection method to …

This paper presents the design of a channel-based asynchronous sequential decoder
implemented with quasi-delay-insensitive templates. The Powermill simulation results in …

This paper presents Investigation of Transient Fault Effects in an asynchronous NoC router.
The experiment is based on simulation-based fault injection method to assess the fault …

The increasing multi-core system complexity with technology scaling introduces new
constraints and challenges to interconnection network design. Consequently, the research …

This paper presents an asynchronous and a synchronous NoC router architecture. The
asynchronous scheme is implemented by the help of CSP-Verilog language and the …

We propose a set of modeling rules and a synthesis method for the design of asynchronous
pipelines. To keep the circuit area and power dissipation of the asynchronous control …

Asynchronous logic is an important topic due to its interesting features of high performance,
low noise and robustness to parameters variations. However, its performance evaluation …