TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
This paper presents the adoption of the triple modular redundancy coupled with the partial
dynamic reconfiguration of field programmable gate arrays to mitigate the effects of soft …
dynamic reconfiguration of field programmable gate arrays to mitigate the effects of soft …
Soft error reliability in advanced CMOS technologies-trends and challenges
D Tang, CH He, YH Li, H Zang, C **ong… - Science China …, 2014 - Springer
With the decrease of the device size, soft error induced by various particles becomes a
serious problem for advanced CMOS technologies. In this paper, we review the evolution of …
serious problem for advanced CMOS technologies. In this paper, we review the evolution of …
A novel design methodology for implementing reliability-aware systems on SRAM-based FPGAs
This paper presents a novel design flow for the implementation of digital systems onto
SRAM-based FPGAs with soft error mitigation properties. Traditional fault …
SRAM-based FPGAs with soft error mitigation properties. Traditional fault …
SEU tolerant latch based on error detection
X She, N Li, J Tong - IEEE transactions on nuclear science, 2012 - ieeexplore.ieee.org
This paper presents an SEU hardened latch that can mitigate SEU based on an error
detection circuit and a multiplexer. During the hold phase, an SEU on an internal node may …
detection circuit and a multiplexer. During the hold phase, an SEU on an internal node may …
Architecture and design flow for a highly efficient structured ASIC
As fabrication process technology continues to advance, mask set costs have become
prohibitively expensive. Structured application specific integrated circuits (sASICs) offer a …
prohibitively expensive. Structured application specific integrated circuits (sASICs) offer a …
Notice of Violation of IEEE Publication Principles: Selective Triple Modular Redundancy for Single Event Upset (SEU) Mitigation
X She, PK Samudrala - 2009 NASA/ESA Conference on …, 2009 - ieeexplore.ieee.org
Notice of Violation of IEEE Publication Principles" Selective Triple Modular Redundancy for
Single Event Upset (SEU) Mitigation" by **aoxuan She, PK Samudrala in the 2009 …
Single Event Upset (SEU) Mitigation" by **aoxuan She, PK Samudrala in the 2009 …
A quantitative analysis of a novel SEU-resistant SHA-2 and HMAC architecture for space missions security
The increasing demand for more secure operation of space missions has led to emergence
of cryptographic mechanisms aboard spacecrafts. However, cryptographic applications are …
of cryptographic mechanisms aboard spacecrafts. However, cryptographic applications are …
SET tolerant dynamic logic
X She, N Li, DO Erstad - IEEE Transactions on Nuclear Science, 2012 - ieeexplore.ieee.org
This paper presents three SET tolerant dynamic logic circuits. The first one uses redundant
PMOS transistors in the precharge circuit and dual redundant pull down networks in the …
PMOS transistors in the precharge circuit and dual redundant pull down networks in the …
Tunable SEU-tolerant latch
X She, N Li, WD Farwell - IEEE transactions on Nuclear …, 2010 - ieeexplore.ieee.org
This paper presents a single event upset (SEU) hardened latch that can mitigate SEU pulses
having a width less than T, where T is the longest anticipated duration of SEUs. The propose …
having a width less than T, where T is the longest anticipated duration of SEUs. The propose …
Single event transient suppressor for flip-flops
X She, N Li, RM Carlson… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
Some single event upset (SEU)-hardened flip-flops cannot mitigate single event transients
(SET) that come from the upstream combinational circuits and propagate to the data inputs …
(SET) that come from the upstream combinational circuits and propagate to the data inputs …