Nanoscale electronic devices based on transition metal dichalcogenides

W Zhu, T Low, H Wang, P Ye, X Duan - 2D Materials, 2019 - iopscience.iop.org
Abstract Two-dimensional (2D) transition metal dichalcogenides (TMDs) have very versatile
chemical, electrical and optical properties. In particular, they exhibit rich and highly tunable …

[HTML][HTML] Ultra-low-power design and hardware security using emerging technologies for Internet of Things

JS Yuan, J Lin, Q Alasad, S Taheri - Electronics, 2017 - mdpi.com
In this review article for Internet of Things (IoT) applications, important low-power design
techniques for digital and mixed-signal analog–digital converter (ADC) circuits are …

Emerging technology-based design of primitives for hardware security

Y Bi, K Shamsi, JS Yuan, PE Gaillardon… - ACM Journal on …, 2016 - dl.acm.org
Hardware security concerns such as intellectual property (IP) piracy and hardware Trojans
have triggered research into circuit protection and malicious logic detection from various …

Coherent Interlayer Tunneling and Negative Differential Resistance with High Current Density in Double Bilayer Graphene–WSe2 Heterostructures

GW Burg, N Prasad, B Fallahazad, A Valsaraj, K Kim… - Nano …, 2017 - ACS Publications
We demonstrate gate-tunable resonant tunneling and negative differential resistance
between two rotationally aligned bilayer graphene sheets separated by bilayer WSe2. We …

Leveraging emerging technology for hardware security-case study on silicon nanowire fets and graphene symfets

Y Bi, PE Gaillardon, XS Hu, M Niemier… - 2014 IEEE 23rd …, 2014 - ieeexplore.ieee.org
Hardware security concerns such as IP piracy and hardware Trojans have triggered
research into circuit protection and malicious logic detection from various design …

Hardware functional obfuscation with ferroelectric active interconnects

T Yu, Y Xu, S Deng, Z Zhao, N Jao, YS Kim… - Nature …, 2022 - nature.com
Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-
complexity with significant area, energy, and delay penalty. In this paper, we propose an …

Performance projections for a reconfigurable tunnel NanoFET

S Blawid, DLM de Andrade, S Mothes… - IEEE Journal of the …, 2017 - ieeexplore.ieee.org
Theoretical performance projections of a reconfigurable tunnel (RT) field-effect transistor
(FET) employing multiple parallel 1-D channels are given. The RT-nanoFET can be …

Spear and shield: Evolution of integrated circuit camouflaging

XY Wang, Q Zhou, YC Cai, G Qu - Journal of Computer Science and …, 2018 - Springer
Intellectual property (IP) protection is one of the hardcore problems in hardware security.
Semiconductor industry still lacks effective and proactive defense to shield IPs from reverse …

Device-circuit interaction and performance benchmarking of tunnel transistor-based ex-OR gates for energy efficient computing

S Shaik - Journal of Circuits, Systems and Computers, 2020 - World Scientific
This paper explores the design and analysis of 20 nm tunnel transistor-based Exclusive-OR
(Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy …

Design of latches and flip-flops using emerging tunneling devices

X Yin, B Sedighi, M Niemier… - 2016 Design, Automation & …, 2016 - ieeexplore.ieee.org
Tunneling field-effect transistors (TFETs) stand out among novel device technologies for low-
power circuits and systems. While some TFETs exhibits behavior similar to MOSFETs, a …