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Nanoscale electronic devices based on transition metal dichalcogenides
Abstract Two-dimensional (2D) transition metal dichalcogenides (TMDs) have very versatile
chemical, electrical and optical properties. In particular, they exhibit rich and highly tunable …
chemical, electrical and optical properties. In particular, they exhibit rich and highly tunable …
[HTML][HTML] Ultra-low-power design and hardware security using emerging technologies for Internet of Things
In this review article for Internet of Things (IoT) applications, important low-power design
techniques for digital and mixed-signal analog–digital converter (ADC) circuits are …
techniques for digital and mixed-signal analog–digital converter (ADC) circuits are …
Emerging technology-based design of primitives for hardware security
Hardware security concerns such as intellectual property (IP) piracy and hardware Trojans
have triggered research into circuit protection and malicious logic detection from various …
have triggered research into circuit protection and malicious logic detection from various …
Coherent Interlayer Tunneling and Negative Differential Resistance with High Current Density in Double Bilayer Graphene–WSe2 Heterostructures
We demonstrate gate-tunable resonant tunneling and negative differential resistance
between two rotationally aligned bilayer graphene sheets separated by bilayer WSe2. We …
between two rotationally aligned bilayer graphene sheets separated by bilayer WSe2. We …
Leveraging emerging technology for hardware security-case study on silicon nanowire fets and graphene symfets
Hardware security concerns such as IP piracy and hardware Trojans have triggered
research into circuit protection and malicious logic detection from various design …
research into circuit protection and malicious logic detection from various design …
Hardware functional obfuscation with ferroelectric active interconnects
Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-
complexity with significant area, energy, and delay penalty. In this paper, we propose an …
complexity with significant area, energy, and delay penalty. In this paper, we propose an …
Performance projections for a reconfigurable tunnel NanoFET
Theoretical performance projections of a reconfigurable tunnel (RT) field-effect transistor
(FET) employing multiple parallel 1-D channels are given. The RT-nanoFET can be …
(FET) employing multiple parallel 1-D channels are given. The RT-nanoFET can be …
Spear and shield: Evolution of integrated circuit camouflaging
Intellectual property (IP) protection is one of the hardcore problems in hardware security.
Semiconductor industry still lacks effective and proactive defense to shield IPs from reverse …
Semiconductor industry still lacks effective and proactive defense to shield IPs from reverse …
Device-circuit interaction and performance benchmarking of tunnel transistor-based ex-OR gates for energy efficient computing
S Shaik - Journal of Circuits, Systems and Computers, 2020 - World Scientific
This paper explores the design and analysis of 20 nm tunnel transistor-based Exclusive-OR
(Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy …
(Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy …
Design of latches and flip-flops using emerging tunneling devices
Tunneling field-effect transistors (TFETs) stand out among novel device technologies for low-
power circuits and systems. While some TFETs exhibits behavior similar to MOSFETs, a …
power circuits and systems. While some TFETs exhibits behavior similar to MOSFETs, a …