Fractional-N frequency synthesizers based on phase-locked loops exhibit spurious tones
(spurs) that result from interactions between the accumulated output of the divider controller …

This paper presents an ultra-low power digitally-assisted analog ring phase-locked loop
(PLL) with a tunable switched capacitor loop filter. The PLL achieves a power efficiency of …

This paper presents the integration of resonant clocking to multi-die architectures to
synchronize individual chiplets connected through an active silicon interposer. The …

Increasing speed and complexity of modern SoCs demand low-jitter clock generators, which
conventionally use LC resonators. But, low power operation at sub-6GHz frequencies …

This paper presents a synthesized fractional-N digital phase-locked loop (PLL) with a
speculative dual-referenced interpolating time-to-digital converter (DI-TDC). The DI-TDC …

This paper proposes a low-power fractional-N all-digital PLL (ADPLL) for the narrow-band
Internet-of-Things applications. Multi-step lock controlling and oscillator tuning word coarse …

A standard-cell-based fractional-N synthesizable phase-locked loop (PLL)[or multiplying-
delay-locked loop (MDLL)] is proposed, where the multiple phases of the three-stage ring …

This article overviews the design considerations and state-of-the-art of the ring voltage-
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …

This article examines the research area of digital phase-locked loops (DPLLs), a critical
component in modern electronic systems, from wireless communication devices to RADAR …

Phase-locked loops (PLLs) are imperative building blocks in wireless system-on-chips
(SoCs) for modulation and clock generation. Their design and implementation typically take …