Silicon CMOS devices beyond scaling

W Haensch, EJ Nowak, RH Dennard… - IBM Journal of …, 2006 - ieeexplore.ieee.org
To a large extent, scaling was not seriously challenged in the past. However, a closer look
reveals that early signs of scaling limits were seen in high-performance devices in recent …

Future of nano CMOS technology

H Iwai - 28th Symposium on Microelectronics Technology and …, 2013 - ieeexplore.ieee.org
Although silicon-based CMOS devices have dominated the integrated circuit applications
over the past few decades, it is expected that the development of CMOS would reach its …

Challenges for future semiconductor manufacturing

H Iwai, K Kakushima, H Wong - International journal of high speed …, 2006 - World Scientific
The downsizing of CMOS devices has been accelerated very aggressively in both
production and research in recent years. Sub-100 nm gate length CMOS large-scale …

Scalability of the si/sub 1-x/ge/sub x/source/drain technology for the 45-nm technology node and beyond

G Eneman, P Verheyen, R Rooyackers… - … on Electron Devices, 2006 - ieeexplore.ieee.org
The authors present a study on the layout dependence of the silicon-germanium
source/drain (Si 1-x Ge x S/D) technology. Experimental results on Si 1-x Ge x S/D …

Methods for forming a transistor and modulating channel stress

S Thirupapuliyur, F Nouri, L Washington - US Patent 8,105,908, 2012 - Google Patents
US8105908B2 - Methods for forming a transistor and modulating channel stress - Google
Patents US8105908B2 - Methods for forming a transistor and modulating channel stress …

Strained semiconductor, devices and systems and methods of formation

L Forbes, PA Farrar - US Patent 7,485,544, 2009 - Google Patents
5,461,243 A 10, 1995 Ek et al. 5,759,898 A 6, 1998 Ek et al. 5,879,996 A 3, 1999 Forbes
5,963,817 A 10, 1999 Chu et al. 6,228,694 B1 5/2001 Doyle et al. 6,242,324 B1 6, 2001 Kub …

Strained semiconductor, devices and systems and methods of formation

L Forbes, PA Farrar - US Patent 7,888,744, 2011 - Google Patents
Division of application No. 1 1/497,632, filed on Aug.(57) 2, 2006, now Pat. No.
7,485,544.(51) Int. Cl. In various method embodiments, a device region is defined in HOIL …

The effects of proton irradiation on 90 nm strained Si CMOS on SOI devices

A Appaswamy, B Jun, RM Diestelhorst… - 2006 IEEE Radiation …, 2006 - ieeexplore.ieee.org
The effects of 63 MeV proton irradiation on 90 nm strained silicon CMOS on insulator is
examined for the first time. The devices show no observable degradation in DC performance …

Stress hybridization for multigate devices fabricated on supercritical strained-SOI (SC-SSOI)

N Collaert, R Rooyackers… - IEEE electron device …, 2007 - ieeexplore.ieee.org
In this letter, we investigate the impact of a hybridized strain technology on the performance
of FinFET-based multigate field-effect transistors (MUGFETs). The technology combines the …

Bonded strained semiconductor with a desired surface orientation and conductance direction

L Forbes - US Patent 8,962,447, 2015 - Google Patents
6,593,625 B2 7/2003 Christiansen et al. 6,603,156 B2 8, 2003 Rim 6,630,713 B2 10/2003
Geusic 6,649,492 B2 11/2003 Chu et al. 6,689,671 B1 2/2004 Yu et al. 6,703,648 B1 3/2004 …