A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection …
This paper presents a fully synthesizable phase-locked loop (PLL) based on injection
locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog …
locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog …
Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
Reconfigurable radios: A possible solution to reduce entry costs in wireless phones
With advances in telecommunications, an increasing number of services rely on high data
rate spectrum access. These critical services include banking, telemedicine, and exchange …
rate spectrum access. These critical services include banking, telemedicine, and exchange …
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration
In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-
locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed …
locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed …
A PVT-robust and low-jitter ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge …
A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock
multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process …
multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process …
A Type-I Sub-Sampling PLL With a Footprint and −255-dB FOM
A dual-loop LC-voltage-controlled oscillator (VCO) based frequency synthesizer, composed
of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, subsampling …
of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, subsampling …
A 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop
Although multiplying delay-locked loops allow clock frequency multiplication with very low
phase noise and jitter, their application has been so far limited to integer-N multiplication …
phase noise and jitter, their application has been so far limited to integer-N multiplication …
Time-mode analog-to-digital conversion using standard cells
Synthesizable all-digital ADCs that can be designed, verified and taped out using a digital
design flow are of interest due to a consequent reduction in design cost and an improved …
design flow are of interest due to a consequent reduction in design cost and an improved …
14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique
Phase-locked loops (PLLs) are a crucial building block in modern Systems-on-Chip (SoCs),
which contain microprocessors, I/O interfaces, memories, power management, and …
which contain microprocessors, I/O interfaces, memories, power management, and …
A low-jitter and low-reference-spur ring-VCO-based switched-loop filter PLL using a fast phase-error correction technique
A low-jitter and low-reference-spur ring-type voltage-controlled oscillator (VCO)-based
switched-loop filter (SLF) phase-locked loop (PLL) is presented. To enhance the capability …
switched-loop filter (SLF) phase-locked loop (PLL) is presented. To enhance the capability …