Variation in performance and power across manufactured parts and their operating
conditions is an accepted reality in modern microelectronic manufacturing processes with …

We show in this paper that multi-layer dependability is an indispensable way to cope with
the increasing amount of technology-induced dependability problems that threaten to …

In this brief, we show that bias temperature instability (BTI) aging of MOS transistors,
together with its detrimental effect for circuit performance and lifetime, presents considerable …

As Moore's Law comes to an end and transistor scaling increasingly falls short in improving
energy efficiency, alternative computing paradigms are direly needed. This need is further …

Variability is one of the major challenges for CMOS in the nano era. Manufacturers test each
circuit sample to ensure that samples that do not meet the desired specification are …

Timing errors of microelectronic circuits occur when the circuit timing specification is
violated, ie, the dynamic delay of circuits exceeds the circuit clock period. With the …

With memories continuing to dominate the area, power, cost and performance of a design,
there is a critical need to provision reliable, high-performance memory bandwidth for …

As the technology scaling enters into the nanoscale regime, soft errors become one of the
major challenging issues for VLSI chips. Susceptibility to soft error is even becoming more …

CMOS miniaturization and timing faults due to factors, such as aging, emphasize that
embedded processor reliability is a major concern. Among the various aging mechanisms …

Scaling to sub-20nm technology nodes changes the nature of reliability effects from abrupt
functional problems to progressive degradation of the performance characteristics of devices …