A survey of FPGA-based LDPC decoders
P Hailes, L Xu, RG Maunder… - … Surveys & Tutorials, 2015 - ieeexplore.ieee.org
Low-density parity check (LDPC) error correction decoders have become popular in
communications systems, as a benefit of their strong error correction performance and their …
communications systems, as a benefit of their strong error correction performance and their …
Unified turbo/LDPC code decoder architecture for deep-space communications
Deep-space communications are characterized by extremely critical conditions; current
standards foresee the usage of both turbo and low-density-parity-check (LDPC) codes to …
standards foresee the usage of both turbo and low-density-parity-check (LDPC) codes to …
Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards
D Suárez, V Fernández, H Posadas… - IEEE Embedded …, 2022 - ieeexplore.ieee.org
Presilicon forward error correction (FEC) decoding hardware is typically designed using
hardware description languages (HDLs). Its verification is a hard task due to its intrinsic …
hardware description languages (HDLs). Its verification is a hard task due to its intrinsic …
Pre-silicon FEC decoding verification on SoC FPGAs
V Fernández, C Abad, Á Álvarez… - IEEE …, 2020 - ieeexplore.ieee.org
Forward error correction (FEC) decoding hardware modules are challenging to verify at pre-
silicon stage, when they are usually described at register-transfer (RT)/logic level with a …
silicon stage, when they are usually described at register-transfer (RT)/logic level with a …
Research of LT code based on key information feedback in deep space communication
H Tian, DF Zhao, YF Yang, R Xue - IEEE Access, 2020 - ieeexplore.ieee.org
CCSDS LDPC code cannot effectively solve the problems of communication interruptions
and high communication error rates in deep space communication. An application scheme …
and high communication error rates in deep space communication. An application scheme …
A reconfigurable 74-140Mbps LDPC decoding system for CCSDS standard
Y Chen, J Wang, S Li, J **e, Q Zhang… - … on Fundamentals of …, 2021 - search.ieice.org
Accumulate Repeat-4 Jagged-Accumulate (AR4JA) codes, which are channel codes
designed for deep-space communications, are a series of QC-LDPC codes. Structures of …
designed for deep-space communications, are a series of QC-LDPC codes. Structures of …
Design and implementation of flexible FPGA-based LDPC decoders
P Hailes - 2018 - eprints.soton.ac.uk
Since their rediscovery in the mid-1990s, Low-Density Parity Check (LDPC) error correction
decoders have been the focus of a great deal of research within the communications …
decoders have been the focus of a great deal of research within the communications …
Accelerating the verification of forward error correction decoders by PCIe FPGA cards
DN Suárez Plata, VM Fernández Solórzano… - 2023 - repositorio.unican.es
Presilicon forward error correction (FEC) decoding hardware is typically designed using
hardware description languages (HDLs). Its verification is a hard task due to its intrinsic …
hardware description languages (HDLs). Its verification is a hard task due to its intrinsic …
Pre-silicon FEC decoding verification on SoC FPGAs
VM Fernández Solórzano, C Abad García… - 2021 - repositorio.unican.es
Forward error correction (FEC) decoding hardware modules are challenging to verify at pre-
silicon stage, when they are usually described at register-transfer (RT)/logic level with a …
silicon stage, when they are usually described at register-transfer (RT)/logic level with a …
[PDF][PDF] VLSI decoding architectures: flexibility, robustness and performance
C Condo - 2014 - tesidottorato.depositolegale.it
The field of communications, both wireless and wired, has seen in the last decades an
unprecedented development. Every day, we use tens of different devices to store, receive …
unprecedented development. Every day, we use tens of different devices to store, receive …