Increasing fault rates in current and future technology nodes coupled with on-chip
components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) …

To achieve higher memory bandwidth in network-based multiprocessor architectures,
multiple dynamic random access memories can be accessed simultaneously. In such …

As multicore systems transition to the many-core realm, the pressure on the interconnection
network is substantially elevated. The network on chip (NoC) is expected to undertake the …

A novel architecture aiming for ideal performance and overhead tradeoff, PVS-NoC (Partial
VC Sharing NoC), is presented. Virtual channel (VC) is an efficient technique to improve …

We introduce a novel heterogeneous NoC router architecture, supporting different link
bandwidths and different number of virtual channels (VCs) per unidirectional port. The NoC …

Due to the inherent burstiness in variable bit rate (VBR) videos, traffic smoothing is often
necessary to improve network utilization and reduce connection costs in VBR video …

Increasing memory parallelism in MPSoCs to provide higher memory bandwidth is achieved
by accessing multiple memories simultaneously. Inasmuch as the response transactions of …

The continuing advances in processing technology result in significant decreases in the
feature size of integrated circuits. This shrinking leads to increases in susceptibility to …

Continuing advances in the processing technology, along with the significant decreases in
the feature size of integrated circuits lead to increases in susceptibility to transient errors and …

Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the
modern on-Chip design. Small optimizations in NoC router architecture can show a …