Recent progress on negative capacitance tunnel FET for low-power applications: Device perspective

AK Upadhyay, SB Rahi, S Tayal, YS Song - Microelectronics Journal, 2022 - Elsevier
In the present-day scenario of low-power electronics, there is a steady and increasing need
for an adequate device that can counteract the power dissipation issue due to the consistent …

Ferroelectric material in triboelectric nanogenerator

Z Zhang, T Wu, E Sun, Y Chen, N Wang - Materials, 2024 - mdpi.com
Ferroelectric materials, with their spontaneous electric polarization, are renewing research
enthusiasm for their deployment in high-performance micro/nano energy harvesting devices …

Investigation of self-heating effects in vertically stacked GAA MOSFET with wrap-around contact

SJ Kang, JH Kim, YS Song, S Go… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
A contact resistance () becomes a major parasitic resistance in highly scaled modern
semiconductor devices. A wrap-around contact (WAC) has been suggested as a promising …

Temporal data learning of ferroelectric HfAlOx capacitors for reservoir computing system

J Lee, S Lee, J Kim, A Emelyanov, S Kim - Journal of Alloys and …, 2024 - Elsevier
Extensive research has been directed towards HfO x-based ferroelectric capacitor in
contrast to perovskite-based ferroelectric capacitors. HfO x-based ferroelectric capacitor …

Performance assessment of dielectrically modulated negative capacitance germanium source vertical tunnel FET biosensor for detection of breast cancer cell lines

K Vanlalawmpuia, P Ghosh - AEU-International Journal of Electronics and …, 2023 - Elsevier
The paper presents a dielectrically modulated negative capacitance Germanium source
vertical tunnel FET (DM-NC-Ge-vTFET) biosensor for detection of non-tumorigenic breast …

Design and performance assessment of a vertical feedback FET

SS Katta, T Kumari, S Das, PK Tiwari - Microelectronics Journal, 2023 - Elsevier
This paper proposes the structure of a vertical PNPN single gated feedback field-effect
transistor (vertical FBFET) and investigates its performance using a TCAD simulator. The …

Analytical compact model of nanowire junctionless gate-all-around MOSFET implemented in verilog-a for circuit simulation

B Smaani, SB Rahi, S Labiod - Silicon, 2022 - Springer
In the present research article, we have proposed an analytical compact model for nanowire
Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor's operation …

Optimization for device figure of merit of ferroelectric tunnel FET using genetic algorithm

N Guenifi, SB Rahi, F Benmahdi… - ECS Journal of Solid …, 2023 - iopscience.iop.org
Tunnel FET is a gate-controlled, field effect transistor, followed band to band tunneling
(BTBT) transport of charge carriers, having low subthreshold swing (SS< 60 Mv decade− 1 …

Steep-subthreshold slope dual gate negative capacitance junction less FET with dead channel: TCAD approach for digital/RF applications

S Chaudhary, B Dewan, C Sahu, M Yadav - Microelectronics Journal, 2022 - Elsevier
In pursuit of lowering power densities and reducing energy efficiency constraints, execution
grid of arising electronic devices are being investigated to track down alternative options for …

A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis

SK Padhi, V Narendar, AK Nishad - Microelectronics Journal, 2024 - Elsevier
This study investigates the effects of temperature on RF/Analog and linearity parameters
using a 3 nm technology node Step-Negative capacitance FinFET (SNC-FinFET) for the first …