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Cell circuit and layout with linear finfet structures
ST Becker - US Patent 9,563,733, 2017 - Google Patents
(57) ABSTRACT A cell circuit and corresponding layout is disclosed to include linear-
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
Finfet transistor circuit
ST Becker, MC Smayling, D Gandhi, J Mali… - US Patent …, 2014 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
ST Becker, MC Smayling - US Patent 8,759,882, 2014 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Circuits with linear finfet structures
ST Becker, MC Smayling, D Gandhi, J Mali… - US Patent …, 2015 - Google Patents
2013-02-22 Assigned to TELA INNOVATIONS, INC. reassignment TELA INNOVATIONS,
INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS) …
INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS) …
Methods for cell phasing and placement in dynamic array architecture and implementation of the same
JR Quandt, ST Becker, D Gandhi - US Patent 8,549,455, 2013 - Google Patents
(57) ABSTRACT A semiconductor chip is defined to include a logic block area having a first
chip level in which layout features are placed according to a first virtual grate, and a second …
chip level in which layout features are placed according to a first virtual grate, and a second …
Integrated circuit cell library for multiple patterning
MC Smayling, ST Becker - US Patent 8,667,443, 2014 - Google Patents
(51) Int. Cl.(57) ABSTRACT G06F 17/50(2006.01) A method is disclosed for defining a
multiple patterned cell (52) US Cl. layout for use in an integrated circuit design. A layout is …
multiple patterned cell (52) US Cl. layout for use in an integrated circuit design. A layout is …
Enforcement of semiconductor structure regularity for localized transistors and interconnect
S Kornachuk, J Mali, C Lambert, ST Becker - US Patent 8,701,071, 2014 - Google Patents
(57) ABSTRACT A global placement grating (GPG) is defined for a chip level to include a set
of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned …
of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned …
Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner …
ST Becker, J Mali, C Lambert - US Patent 8,847,329, 2014 - Google Patents
First worldwide family litigation filed litigation Critical https://patents. darts-ip. com/? family=
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Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track
ST Becker, J Mali, C Lambert - US Patent 8,836,045, 2014 - Google Patents
First worldwide family litigation filed litigation Critical https://patents. darts-ip. com/? family=
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Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track
ST Becker, J Mali, C Lambert - US Patent 8,735,995, 2014 - Google Patents
First worldwide family litigation filed litigation Critical https://patents. darts-ip. com/? family=
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