Multi-core processor system, monitoring control method, and computer product
T Suzuki, K Yamashita, H Yamauchi… - US Patent …, 2016 - Google Patents
BACKGROUND A technique called checkpoint/restart has been disclosed as a technique for
improving the reliability of computer systems (see, for example,“A Survey of …
improving the reliability of computer systems (see, for example,“A Survey of …
Precise excecution of versioned store instructions
Z Radovic, JC Smolens, RT Golla, PJ Jordan… - US Patent …, 2017 - Google Patents
Techniques for executing versioned memory access instructions. In one embodiment, a
processor is configured to execute versioned store instructions of a first thread within a first …
processor is configured to execute versioned store instructions of a first thread within a first …
Split-level history buffer in a computer processing unit
HQ Le, DQ Nguyen, DR Terry - US Patent 9,524,171, 2016 - Google Patents
Embodiments of the present invention provide a system, a method, and a computer program
product for a split level history buffer in a central processing unit. A history buffer is split into …
product for a split level history buffer in a central processing unit. A history buffer is split into …
Split-level history buffer in a computer processing unit
HQ Le, DQ Nguyen, DR Terry - US Patent 9,940,139, 2018 - Google Patents
A split level history buffer in a central processing unit is provided. A history buffer is split into
a first portion and a second portion. An instruction fetch unit fetches and tags instructions. A …
a first portion and a second portion. An instruction fetch unit fetches and tags instructions. A …
Debugging data processing transactions
S Diestelhorst, MJ Williams, RR Grisenthwaite… - US Patent …, 2019 - Google Patents
A data processing system supporting execution of transactions comprising one or more
program instructions that execute to generate speculative updates is provided. The …
program instructions that execute to generate speculative updates is provided. The …
Programmable load replay precluding mechanism
GM Col, C Eddy, GG Henry - US Patent 10,114,794, 2018 - Google Patents
An apparatus including first and second reservation stations. The first reservation station
dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction …
dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction …
Split-level history buffer in a computer processing unit
HQ Le, DQ Nguyen, DR Terry - US Patent 9,851,979, 2017 - Google Patents
A split level history buffer in a central processing unit is provided. A first instruction and a
second instruction are fetched, tagged, and the first instruction is stored an entry of a register …
second instruction are fetched, tagged, and the first instruction is stored an entry of a register …
Split-level history buffer in a computer processing unit
HQ Le, DQ Nguyen, DR Terry - US Patent 10,241,800, 2019 - Google Patents
US10241800B2 - Split-level history buffer in a computer processing unit - Google Patents
US10241800B2 - Split-level history buffer in a computer processing unit - Google Patents …
US10241800B2 - Split-level history buffer in a computer processing unit - Google Patents …
Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
GM Col, C Eddy, GG Henry - US Patent 10,089,112, 2018 - Google Patents
An apparatus including first and second reservation stations. The first reservation station
dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction …
dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction …