Evaluation of variability using schmitt trigger on full adders layout

LB Moraes, AL Zimpeck, C Meinhardt, R Reis - Microelectronics reliability, 2018 - Elsevier
The aggressive technology and voltage scaling which modern digital circuits are facing
introduce a higher influence in metrics, as performance and power consumption, due to …

Design and Performance Analysis of 1‐Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology

A Abdul Tahrim, HC Chin, CS Lim… - Journal of …, 2015 - Wiley Online Library
The scaling process of the conventional 2D‐planar metal‐oxide semiconductor field‐effect
transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm …

[PDF][PDF] A low-voltage and low-power two-stage operational amplifier using FinFET transistors

VB Rahin, AB Rahin - International Academic Journal of Science …, 2016 - researchgate.net
In this paper, a high gain and low-power FinFET-based amplifier with independent gates is
proposed and its design and simulation are performed by HSPICE software and FinFET …

Soft Error Impact on FinFET and CMOS XOR Logic Gates

RNM Oliveira, C Meinhardt - Journal of Integrated Circuits and Systems, 2020 - jics.org.br
With the advance of computer systems, XORgates design became essential on arithmetic
circuits. Atnanometer nodes, despite the electrical characterization, de-signers must to …

Reliability challenges in finfets

A Zimpeck, C Meinhardt, L Artola, R Reis… - … Process Variability and …, 2021 - Springer
The technology scaling and the adoption of FinFET devices brought several benefits, but
some drawbacks were also introduced at each technology node. This chapter starts by …

Design and implementation of a 1-bit FinFET full adder cell for ALU in subthreshold region

ABA Tahrim, MLP Tan - 2014 IEEE International Conference on …, 2014 - ieeexplore.ieee.org
The FinFET based Full Adder in various cell designs is investigated in terms of performance
and energy efficiency. Additionally, the performance of the FinFET Full Adder in the …

Minimum energy FinFET schmitt trigger design considering process variability

LB Moraes, AL Zimpeck, C Meinhardt… - 2019 IFIP/IEEE 27th …, 2019 - ieeexplore.ieee.org
The emergence of IoT alongside with the increased process variability impact in modern
technology nodes, is the main reason to control variability impact over metrics. Given the …

Investigation of robust full adder cell in 16-nm CMOS technology node

V Dokania, A Imran, A Islam - IMPACT-2013, 2013 - ieeexplore.ieee.org
This paper investigates the most popular 1-bit CMOS full adder circuits to examine them for
robustness and consistency against adverse variations in process parameters using ultra …

Design, Analysis and Optimization of CMOS Full Adder Based FinFET 10 nm

L Abdelaziz, B Khaled… - 2023 13th International …, 2023 - ieeexplore.ieee.org
The miniaturization of transistors at the Nanometric scale has caused adverse effects on the
performance of devices. Researchers have proposed new structures such as FinFET with …

Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells

AL Zimpeck - 2019 - hal.science
Process variability mitigation and radiation hardness are relevant reliability requirements as
chip manufacturing advances more in-depth into the nanometer regime. The parameter yield …