Computer architects have been studying the dynamically reconfigurable computer
(Schaumont, Verbauwhede, Keutzer, and Sarrafzadeh,“A Quick Safari through the …

(57) ABSTRACT A logic chip has a plurality of individually addressable resource blocks
each of the resource blocks having logic circuitry, and a communication bar extending …

Reconfigurable systems have pervaded nearly all fields of computation and will continue to
do so for the foreseeable future. Reconfigurable System Design and Verification provides a …

The regular structure and addressing scheme for the Virtex-IIfamily of field programmable
gate arrays (FPGAs) allows the relocation of partial bitstreams through direct bitstream …

This paper presents a tool for Virtex II (Pro) FPGA partial bitstream manipulation suited for
reconfigurable control systems with limited computing resources. The basics for partial …

This paper presents techniques for generating on-chip buses suitable for dynamically
integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The …

In this paper, we present and analyze a sophisticated communication architecture that
allows to integrate many different modules into a system by FPGA reconfiguration at runtime …

Platform-based designed SoC includes one or more processors, RTOS, intellectual property
blocks, memories and an interconnection infrastructure. An associated advantage of …

(57) ABSTRACT A logic chip has a plurality of individually-addressable resource blocks,
each comprising logic circuitry. The logic chip also has a bus comprising a plurality of bus …

An approach to modeling complex real-world data such as biomedical signals is to develop
pattern recognition techniques and robust features that capture the relevant information. In …