Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

WM Weber, T Mikolajick - Reports on Progress in Physics, 2017 - iopscience.iop.org
Research in the field of electronics of 1D group-IV semiconductor structures has attracted
increasing attention over the past 15 years. The exceptional combination of the unique 1D …

A pathway to improve short channel effects of junctionless based FET's after incorporating technology boosters: a review

V Narula, M Agarwal, S Verma - Engineering Research Express, 2024 - iopscience.iop.org
Abstract The Short Channel Effects (SCE) are becoming more prominent in Complementary
Metal Oxide Semiconductor (CMOS) circuits with the introduction of nanoscale Metal Oxide …

The junctionless transistor

JP Colinge - Emerging devices for low-power and high …, 2018 - taylorfrancis.com
The junctionless transistor consists of a piece of uniformly doped semiconductor with a gate
placed between the source and drain contacts and is, therefore, the simplest transistor …

Comparison of logic performance of CMOS circuits implemented with junctionless and inversion-mode FinFETs

S Guin, M Sil, A Mallik - IEEE Transactions on Electron Devices, 2017 - ieeexplore.ieee.org
In this paper, we report the logic performance of CMOS circuits implemented with n-and p-
channel junctionless (JL) FinFETs. A one-to-one comparison of the performance is made …

Revisiting the do** requirement for low power junctionless MOSFETs

MS Parihar, A Kranti - Semiconductor Science and Technology, 2014 - iopscience.iop.org
In this work, we revisit the requirement of higher channel do** (≥ 10 19 cm− 3) in
junctionless (JL) double gate MOSFETs. It is demonstrated that moderately doped (10 18 …

Junctionless versus inversion-mode gate-all-around nanowire transistors from a low-frequency noise perspective

E Simoen, A Veloso, P Matagne… - … on Electron Devices, 2018 - ieeexplore.ieee.org
The low-frequency noise behavior of junction-less (JL) gate-all-around (GAA) nanowire
(NW) FETs has been investigated and compared with similar inversion-mode (IM) devices. It …

Computational study of effects of surface roughness and impurity scattering in Si double-gate junctionless transistors

M Ichii, R Ishida, H Tsuchiya… - … on Electron Devices, 2015 - ieeexplore.ieee.org
Electron transport in Si double-gate junctionless transistors (JLTs) is simulated on the basis
of the multisubband Monte Carlo method, considering acoustic phonons, intervalley …

Analysis and compact modeling of gate capacitance in organic thin-film transistors

H Cortes-Ordonez, S Jacob, F Mohamed… - … on Electron Devices, 2019 - ieeexplore.ieee.org
In this paper, we target the compact capacitance modeling of organic thin-film transistor
(OTFTs) valid from depletion to accumulation regime taking into account the frequency …

Physically based evaluation of electron mobility in ultrathin-body double-gate junctionless transistors

K Wei, L Zeng, J Wang, G Du… - IEEE electron device letters, 2014 - ieeexplore.ieee.org
In this letter, we presented theoretical results on the low-field electron mobility of ultrathin-
body double-gate junctionless transistors. A 1D Poisson-Schrödinger problem …

High frequency top-down junction-less silicon nanowire resonators

A Koumela, S Hentz, D Mercier, C Dupré… - …, 2013 - iopscience.iop.org
We report here the first realization of top-down silicon nanowires (SiNW) transduced by both
junction-less field-effect transistor (FET) and the piezoresistive (PZR) effect. The suspended …