The last line of defense in the cache hierarchy before going to off-chip memory is very critical
in chip multiprocessors (CMPs) from both the performance and power perspectives. We …

This book studies hardware and software specifications at algorithmic level from the point of
measuring and extracting the potential parallelism hidden in them. It investigates the …

FPGAs play an increasing role in the reconfigurable accelerator landscape. A key challenge
in designing FPGA-based systems is partitioning computation between processor cores and …

Large dataflow designs are a result of behavioral specification of modern complex digital
systems and/or a result of unfolding and transforming looped and branched programs. Since …

While research on the design of heterogeneous concurrent systems has a long and rich
history, a unified design methodology and tool support has not emerged so far, and thus the …

This paper presents the main features of the TURNUS co-exploration environment, an
unified design space exploration framework suitable for heterogeneous parallel systems …

The trade-off between throughput and memory constraints is a common design problem in
embedded systems, and especially for streaming applications, where the memory in …

To increase performance and efficiency, systems use FPGAs as reconfigurable accelerators.
A key challenge in designing these systems is partitioning computation between processors …

This paper introduces a new methodology for pipeline synthesis with applications to data
flow high-level system design. The pipeline synthesis is applied to dataflow programs whose …

In this paper we propose a design methodology to partition dataflow applications on a multi
clock domain architecture. This work shows how starting from a high level dataflow …