Parmibench-an open-source benchmark for embedded multiprocessor systems

SMZ Iqbal, Y Liang, H Grahn - IEEE Computer Architecture …, 2010 - ieeexplore.ieee.org
Multicore processors are the main computing platform in laptops, desktop, and servers
today, and are making their way into the embedded systems market also. Using benchmarks …

[BOK][B] Mikrocontroller und Mikroprozessoren

U Brinkschulte, T Ungerer - 2010 - Springer
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[PDF][PDF] An evaluation of dynamic partial reconfiguration for signal and image processing in professional electronics applications

P Manet, D Maufroid, L Tosi, G Gailliard… - EURASIP Journal on …, 2009 - Springer
Signal and image processing applications require a lot of computing resources. For low-
volume applications like in professional electronics applications, FPGA are used in …

A direct coherence protocol for many-core chip multiprocessors

A Ros, ME Acacio, JM Garcia - IEEE Transactions on Parallel …, 2010 - ieeexplore.ieee.org
Future many-core CMP designs that will integrate tens of processor cores on-chip will be
constrained by area and power. Area constraints make impractical the use of a bus or a …

Processor virtualization and split compilation for heterogeneous multicore embedded systems

A Cohen, E Rohou - Proceedings of the 47th Design Automation …, 2010 - dl.acm.org
Embedded multiprocessors have always been heterogeneous, driven by the power-
efficiency and compute-density of hardware specialization. We aim to achieve portability and …

DiCo-CMP: Efficient cache coherency in tiled CMP architectures

A Ros, ME Acacio, JM García - 2008 IEEE International …, 2008 - ieeexplore.ieee.org
Future CMP designs that will integrate tens of processor cores on-chip will be constrained by
area and power. Area constraints make impractical the use of a bus or a crossbar as the on …

SpiceC: scalable parallelism via implicit copying and explicit commit

M Feng, R Gupta, Y Hu - Proceedings of the 16th ACM symposium on …, 2011 - dl.acm.org
In this paper we present an approach to parallel programming called SpiceC. SpiceC
simplifies the task of parallel programming through a combination of an intuitive computation …

A hard real-time capable multi-core SMT processor

M Paolieri, J Mische, S Metzlaff, M Gerdes… - ACM Transactions on …, 2013 - dl.acm.org
Hard real-time applications in safety critical domains require high performance and time
analyzability. Multi-core processors are an answer to these demands, however task …

Adaptive cache coherence mechanisms with producer–consumer sharing optimization for chip multiprocessors

A Kayi, O Serres, T El-Ghazawi - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
In chip multiprocessors (CMPs), maintaining cache coherence can account for a major
performance overhead. Write-invalidate protocols adapted by most CMPs generate high …

Finding an upper bound on the increase in execution time due to contention on the memory bus in COTS-based multicore systems

B Andersson, A Easwaran, J Lee - ACM Sigbed Review, 2010 - dl.acm.org
Contention on the memory bus in COTS based multicore systems is becoming a major
determining factor of the execution time of a task. Analyzing this extra execution time is non …