Robust approach towards wearable power efficient transistors with low subthreshold swing

E Elahi, M Suleman, S Nisar, PR Sharma… - Materials Today …, 2023 - Elsevier
For emerging wearable chip-based electronics, power loss is a critical concern for micro-
nano electronic circuits due to high subthreshold swing (SS) value of 60 mV dec− 1 for the …

Cold source field-effect transistors: Breaking the 60-mV/decade switching limit at room temperature

S Wang, J Wang, T Zhi, J Xue, D Chen, L Wang… - Physics Reports, 2023 - Elsevier
With the size of devices continuously shrinking, power consumption has become one of the
most critical issues concerning modern integrated circuits, which can be reduced by …

Impact of work function variation for enhanced electrostatic control with suppressed ambipolar behavior for dual gate L-TFET

P Singh, DS Yadav - Current Applied Physics, 2022 - Elsevier
The favorable electrostatic potential and tunneling underneath the overall gate region, which
prevents legitimate source to drain tunneling, controllability over the gate is assisted in …

Ge-source based L-shaped tunnel field effect transistor for low power switching application

S Chander, SK Sinha, R Chaudhary, A Singh - Silicon, 2021 - Springer
In this work, the performance of the heterojunction L-Tunnel Field Effect Transistor (LTFET)
has been analyzed with different engineering techniques such as bandgap engineering …

Physics based analysis of a high-performance dual line tunneling TFET with reduced corner effects

T Ashok, CK Pandey - Physica Scripta, 2024 - iopscience.iop.org
To improve the DC and analog/HF performance, a novel dual line tunneling based TFET
(DLT-ES-TFET) with elevated source and L-shaped pocket is proposed in this manuscript. In …

Extended Gate to source overlap Heterojunction Vertical TFET: Design, analysis, and optimization with process parameter variations

T Chawla, M Khosla, B Raj - Materials Science in Semiconductor …, 2022 - Elsevier
This report highlights the simulated results of Extended gate to source overlap
Heterojunction Vertical Tunnel field effect transistor (EGH-VTFET) for low-power and high …

Optimal design and performance analysis of vertically stacked nanosheet tunnel field effect transistor

S Anthoniraj, K Saravanan, AS Vinay Raj, NA Vignesh - Silicon, 2022 - Springer
Tunneling field effect transistors (TFETs) have been proposed as switches for low-power
integrated circuits. A negative-capacitance vertical-tunnel FET that improves vertical …

Assessing the Impact of Drain Underlap Perspective Approach to Investigate DC/RF to Linearity Behavior of L-Shaped TFET

P Singh, DS Yadav - Silicon, 2022 - Springer
Controllability over the gate is facilitated in vertical TFET formations because of the favorable
electrostatic potential and tunneling under the entire gate region, inhibiting direct source to …

Steep subthreshold swing Double-Gate tunnel FET using source pocket engineering: Design guidelines

N Yadav, S Jadav, G Saini - Micro and Nanostructures, 2024 - Elsevier
In this work, we propose a promising source engineered Double-Gate (DG) Tunnel Field
Effect Transistor (TFET) device capable of providing remarkably low value of Subthreshold …

Raised Ge-Source with n+ pocket and recessed drain line TFET: A proposal for biosensing applications

A Anam, SI Amin, D Prasad - Materials Science and Engineering: B, 2024 - Elsevier
In this paper, we present a novel raised Ge-source with an n+ pocket and recessed drain
line Tunnel Field-Effect Transistor (TFET). It offers enhanced performance for potential …