Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test

E Afacan, N Lourenço, R Martins, G Dündar - Integration, 2021 - Elsevier
Rapid developments in semiconductor technology have substantially increased the
computational capability of computers. As a result of this and recent developments in theory …

A review of machine learning techniques in analog integrated circuit design automation

R Mina, C Jabbour, GE Sakr - Electronics, 2022 - mdpi.com
Analog integrated circuit design is widely considered a time-consuming task due to the
acute dependence of analog performance on the transistors' and passives' dimensions. An …

Curved fatigue crack growth prediction under variable amplitude loading by artificial neural network

B Wang, L **e, J Song, B Zhao, C Li, Z Zhao - International Journal of …, 2021 - Elsevier
The focus of this study is to predict curved crack FCG failure under variable amplitude load
effectively and accurately. Based on the artificial neural network (ANN) and FCG path/life …

Learning to design analog circuits to meet threshold specifications

D Krylov, P Khajeh, J Ouyang… - International …, 2023 - proceedings.mlr.press
Automated design of analog and radio-frequency circuits using supervised or reinforcement
learning from simulation data has recently been studied as an alternative to manual expert …

Artificial neural network model for design optimization of 2-stage op-amp

MV Harsha, BP Harish - … Symposium on VLSI Design and Test …, 2020 - ieeexplore.ieee.org
The existence of multi-dimensional tradeoffs among performance metrics is an impediment
to the development of reliable Electronic Design Automation (EDA) tools for the design of …

Design of optimal CMOS analog amplifier circuits using a hybrid evolutionary optimization technique

BP De, KB Maji, R Kar, D Mandal… - Journal of Circuits …, 2018 - World Scientific
This paper proposes an efficient design technique for two commonly used VLSI circuits,
namely, CMOS current mirror load-based differential amplifier circuit and CMOS two-stage …

Reinforcement Learning for Analog Sizing Optimization

M Chevalier, S Trochut, R Guizzetti… - … and Applications to …, 2023 - ieeexplore.ieee.org
This paper proposes a novel adaptation of Machine Learning (ML) techniques based on
reinforcement learning for the resolution of analog sizing optimization problems. The paper …

Machine Learning for Testing of VLSI Circuit

A Choubey, SB Choubey - VLSI and Hardware …, 2021 - api.taylorfrancis.com
Digital and analog devices and circuits are basic electronic components in the widest type of
electronic devices. In addition to consumer electronics markets, the IC industry more than …

Enhancing Transistor Sizing in Analog IC Design using a Circuit-Focused Semi-Supervised Learning

R Mina, GE Sakr, H Nassif - 2023 IEEE 4th International …, 2023 - ieeexplore.ieee.org
This work investigates the application of artificial neural networks to predict transistor
dimensions in analog integrated circuits using semi-supervised learning. Traditionally …

Evolutionary computation based sizing technique of nulling resistor compensation based cmos two-stage op-amp circuit

BP De, KB Maji, R Kar, D Mandal… - International Journal of …, 2017 - World Scientific
This article explores the comparative optimizing efficiency between two PSO variants,
namely, Craziness based PSO (CRPSO) and PSO with an Aging Leader and Challengers …