A Survey on Thwarting Memory Corruption in RISC-V

M Brohet, F Regazzoni - ACM Computing Surveys, 2023 - dl.acm.org
With embedded devices becoming more pervasive and entrenched in society, it is
paramount to keep these systems secure. A threat plaguing these systems consists of …

A review of security issues and solutions for precision health in Internet-of-Medical-Things systems

N Li, M Xu, Q Li, J Liu, S Bao, Y Li, J Li… - Security and …, 2023 - sands.edpsciences.org
Precision medicine provides a holistic perspective of an individual's health, including
genetic, environmental, and lifestyle aspects to realize individualized therapy. The …

Hardware-based always-on heap memory safety

Y Kim, J Lee, H Kim - 2020 53rd Annual IEEE/ACM …, 2020 - ieeexplore.ieee.org
Memory safety violations, caused by illegal use of pointers in unsafe programming
languages such as C and C++, have been a major threat to modern computer systems …

Cornucopia: Temporal safety for CHERI heaps

NW Filardo, BF Gutstein, J Woodruff… - … IEEE Symposium on …, 2020 - ieeexplore.ieee.org
Use-after-free violations of temporal memory safety continue to plague software systems,
underpinning many high-impact exploits. The CHERI capability system shows great promise …

Cryptographic capability computing

M LeMay, J Rakshit, S Deutsch, DM Durham… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
Capability architectures for memory safety have traditionally required expanding pointers
and radically changing microarchitectural structures throughout processors, while only …

Capability hardware enhanced RISC instructions: CHERI instruction-set architecture (version 7)

RNM Watson, PG Neumann, J Woodruff, M Roe… - 2019 - cl.cam.ac.uk
This technical report describes CHERI ISAv7, the seventh version of the Capability
Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA) being …

Mswasm: Soundly enforcing memory-safe execution of unsafe code

AE Michael, A Gollamudi, J Bosamiya… - Proceedings of the …, 2023 - dl.acm.org
Most programs compiled to WebAssembly (Wasm) today are written in unsafe languages
like C and C++. Unfortunately, memory-unsafe C code remains unsafe when compiled to …

An introduction to CHERI

RNM Watson, SW Moore, P Sewell, PG Neumann - 2019 - cl.cam.ac.uk
Abstract CHERI (Capability Hardware Enhanced RISC Instructions) extends conventional
processor Instruction-Set Architectures (ISAs) with architectural capabilities to enable fine …

CAPSTONE: a capability-based foundation for trustless secure memory access

JZ Yu, C Watt, A Badole, TE Carlson… - 32nd USENIX Security …, 2023 - usenix.org
Capability-based memory isolation is a promising new architectural primitive. Software can
access low-level memory only via capability handles rather than raw pointers, which …

No-FAT: Architectural support for low overhead memory safety checks

MTI Ziad, MA Arroyo, E Manzhosov… - 2021 ACM/IEEE 48th …, 2021 - ieeexplore.ieee.org
Memory safety continues to be a significant software reliability and security problem, and low
overhead and low complexity hardware solutions have eluded computer designers. In this …