A Survey on Thwarting Memory Corruption in RISC-V
M Brohet, F Regazzoni - ACM Computing Surveys, 2023 - dl.acm.org
With embedded devices becoming more pervasive and entrenched in society, it is
paramount to keep these systems secure. A threat plaguing these systems consists of …
paramount to keep these systems secure. A threat plaguing these systems consists of …
A review of security issues and solutions for precision health in Internet-of-Medical-Things systems
Precision medicine provides a holistic perspective of an individual's health, including
genetic, environmental, and lifestyle aspects to realize individualized therapy. The …
genetic, environmental, and lifestyle aspects to realize individualized therapy. The …
Hardware-based always-on heap memory safety
Memory safety violations, caused by illegal use of pointers in unsafe programming
languages such as C and C++, have been a major threat to modern computer systems …
languages such as C and C++, have been a major threat to modern computer systems …
Cornucopia: Temporal safety for CHERI heaps
NW Filardo, BF Gutstein, J Woodruff… - … IEEE Symposium on …, 2020 - ieeexplore.ieee.org
Use-after-free violations of temporal memory safety continue to plague software systems,
underpinning many high-impact exploits. The CHERI capability system shows great promise …
underpinning many high-impact exploits. The CHERI capability system shows great promise …
Cryptographic capability computing
Capability architectures for memory safety have traditionally required expanding pointers
and radically changing microarchitectural structures throughout processors, while only …
and radically changing microarchitectural structures throughout processors, while only …
Capability hardware enhanced RISC instructions: CHERI instruction-set architecture (version 7)
RNM Watson, PG Neumann, J Woodruff, M Roe… - 2019 - cl.cam.ac.uk
This technical report describes CHERI ISAv7, the seventh version of the Capability
Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA) being …
Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA) being …
Mswasm: Soundly enforcing memory-safe execution of unsafe code
Most programs compiled to WebAssembly (Wasm) today are written in unsafe languages
like C and C++. Unfortunately, memory-unsafe C code remains unsafe when compiled to …
like C and C++. Unfortunately, memory-unsafe C code remains unsafe when compiled to …
An introduction to CHERI
Abstract CHERI (Capability Hardware Enhanced RISC Instructions) extends conventional
processor Instruction-Set Architectures (ISAs) with architectural capabilities to enable fine …
processor Instruction-Set Architectures (ISAs) with architectural capabilities to enable fine …
CAPSTONE: a capability-based foundation for trustless secure memory access
Capability-based memory isolation is a promising new architectural primitive. Software can
access low-level memory only via capability handles rather than raw pointers, which …
access low-level memory only via capability handles rather than raw pointers, which …
No-FAT: Architectural support for low overhead memory safety checks
Memory safety continues to be a significant software reliability and security problem, and low
overhead and low complexity hardware solutions have eluded computer designers. In this …
overhead and low complexity hardware solutions have eluded computer designers. In this …