Methods for GAA I/O formation by selective epi regrowth

B Colombeau, M Bauer, NA Siddiqui… - US Patent 11,393,916, 2022‏ - Google Patents
Electronic devices and methods of forming electronic devices with gate-all-around non-I/O
devices and finlike structures for I/O devices are described. A plurality of dummy gates is …

Transistor gate structures and methods of forming the same

SY Lin, C Chen-**, H Lee, CH Lin - US Patent 12,142,655, 2024‏ - Google Patents
In an embodiment, a device includes: an isolation region; nanostructures protruding above a
top surface of the isolation region; a gate structure wrapped around the nanostructures, the …

Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits

MI Gardner, HJ Fulford - US Patent 11,222,964, 2022‏ - Google Patents
Microfabrication of a collection of transistor types on mul tiple transistor planes in which both
HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a …

Nanosheet transistor with self-aligned dielectric pillar

R **e, K Cheng, J Frougier - US Patent 11,195,746, 2021‏ - Google Patents
Embodiments of the present invention are directed to a semiconductor structure and a
method for forming a semi conductor structure having a self-aligned dielectric pillar for …

Nanosheet device architecture for cell-height scaling

CW Hsu, KC Chiang, ML Huang, LK Chu… - US Patent …, 2024‏ - Google Patents
2021-11-23 Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF …

Variable sheet forkFET device

J Frougier, R **e, K Cheng, C Park - US Patent 11,527,535, 2022‏ - Google Patents
An embodiment of the invention may include a forkFET semiconductor structure, and the
method of forming said structure. The structure may include a first FET device and a second …

Gate isolation structure

JC You, CH Chang, KC Chiang, KL Cheng… - US Patent …, 2022‏ - Google Patents
A semiconductor device according to the present disclosure includes a first gate structure
and a second gate structure aligned along a direction, a first metal layer disposed over the …

Gate isolation structure

JC You, CH Chang, KC Chiang, KL Cheng… - US Patent …, 2024‏ - Google Patents
2022-07-22 Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF …

Integrated circuit device

Y Junggil, M Kim, KOH Donghyi - US Patent 11,710,739, 2023‏ - Google Patents
US11710739B2 - Integrated circuit device - Google Patents US11710739B2 - Integrated
circuit device - Google Patents Integrated circuit device Download PDF Info Publication …

Field effect transistor with fin isolation structure and method

J Yi-Ruei, KT Pan, KC Chiang, CH Wang - US Patent 12,080,776, 2024‏ - Google Patents
A device includes a substrate and a fin isolation structure between a first gate structure and
a second gate structure. The first gate structure wraps around a first vertical stack of …