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Methods for fault tolerance in networks-on-chip
Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …
Reliable on-chip systems in the nano-era: Lessons learnt and future trends
Reliability concerns due to technology scaling have been a major focus of researchers and
designers for several technology nodes. Therefore, many new techniques for enhancing and …
designers for several technology nodes. Therefore, many new techniques for enhancing and …
Underdesigned and opportunistic computing in presence of hardware variability
Microelectronic circuits exhibit increasing variations in performance, power consumption,
and reliability parameters across the manufactured parts and across use of these parts over …
and reliability parameters across the manufactured parts and across use of these parts over …
Moore's law: The first ending and a new beginning
Moore's law has accurately predicted roughly biennial doubling of component capacity at
minimal cost for almost 50 years. Recent flash memory scaling exhibits increased density …
minimal cost for almost 50 years. Recent flash memory scaling exhibits increased density …
Workload dependent NBTI and PBTI analysis for a sub-45nm commercial microprocessor
This paper analyzes aging effects on various design hierarchies of a sub-45nm commercial
processor running realistic applications. Dependencies of aging effects on switching-activity …
processor running realistic applications. Dependencies of aging effects on switching-activity …
At-speed distributed functional testing to detect logic and delay faults in NoCs
In this work, we propose a distributed functional test mechanism for NoCs which scales to
large-scale networks with general topologies and routing algorithms. Each router and its …
large-scale networks with general topologies and routing algorithms. Each router and its …
Robust system design to overcome CMOS reliability challenges
Today's mainstream electronic systems typically assume that transistors and interconnects
operate correctly over their useful lifetime. With enormous complexity and significantly …
operate correctly over their useful lifetime. With enormous complexity and significantly …
Estimating circuit aging due to BTI and HCI using ring-oscillator-based sensors
The performance of nanometer-scale circuits is adversely affected by aging induced by bias
temperature instability (BTI) and hot carrier injection (HCI). Both BTI and HCI impact …
temperature instability (BTI) and hot carrier injection (HCI). Both BTI and HCI impact …
Assessment of circuit optimization techniques under NBTI
This paper conducts a comprehensive study on existing circuit optimization techniques
against NBTI, degradation mechanism that has become a critical reliability issue for nano …
against NBTI, degradation mechanism that has become a critical reliability issue for nano …
Fine-grained aging-induced delay prediction based on the monitoring of run-time stress
Run-time solutions based on online monitoring and adaptation are required for resilience in
nanoscale integrated circuits, as design-time solutions and guard bands are no longer …
nanoscale integrated circuits, as design-time solutions and guard bands are no longer …