Double-layer stepped Si (1 0 0) surfaces prepared in As-rich CVD ambience
Low-defect III-V integration on Si (1 0 0) requires atomically well-ordered heterointerfaces.
To this end, we study the interaction of As with Si (1 0 0) surfaces and the formation of …
To this end, we study the interaction of As with Si (1 0 0) surfaces and the formation of …
Tensile strain in arsenic heavily doped Si
G Borot, L Rubaldo, L Clement, R Pantel… - Journal of Applied …, 2007 - pubs.aip.org
In this paper we highlight the existence of tensile stress in heavily arsenic-doped epitaxial
silicon (Si: As) prepared by low pressure chemical vapor deposition. Despite the large size …
silicon (Si: As) prepared by low pressure chemical vapor deposition. Despite the large size …
High-performance varactor diodes integrated in a silicon-on-glass technology
High-performance low-loss boron-passivated Schottky varactor diodes have been fabricated
in a silicon-on-glass substrate transfer technology, using laser-annealed back-wafer …
in a silicon-on-glass substrate transfer technology, using laser-annealed back-wafer …
Abrupt phosphorus profiles in Si: Effects of temperature and substitutional carbon on phosphorus autodo**
DV Singh, JL Hoyt, JF Gibbons - Journal of the Electrochemical …, 2003 - iopscience.iop.org
The effect of growth temperature and substitutional carbon on phosphorus autodo** in Si
grown by low pressure rapid thermal chemical vapor deposition was investigated. In the …
grown by low pressure rapid thermal chemical vapor deposition was investigated. In the …
Reduction of UHF power transistor distortion with a nonuniform collector do** profile
The linearity of a class-A, bipolar UHF power transistor is investigated. The device is
intended for transmission of signals with multiple (TV) channels. Mixing between the various …
intended for transmission of signals with multiple (TV) channels. Mixing between the various …
Arsenic-spike epilayer technology applied to bipolar transistors
For the first time, epilayers with an arsenic-doped spike of 50 nm width have been grown
and used in silicon bipolar junction transistors (BJTs). The epilayer has been optimized such …
and used in silicon bipolar junction transistors (BJTs). The epilayer has been optimized such …
Controlled growth of non-uniform arsenic profiles in silicon reduced-pressure chemical vapor deposition epitaxial layers
M Popadić, TLM Scholtes, W De Boer… - Journal of electronic …, 2009 - Springer
An empirical model of As surface segregation during reduced-pressure chemical vapor
deposition Si epitaxy is presented. This segregation mechanism determines the resulting …
deposition Si epitaxy is presented. This segregation mechanism determines the resulting …
Method for fabricating a semiconductor substrate
A Drouin, B Aspar, C Desrumaux, O Ledoux… - US Patent …, 2013 - Google Patents
The invention relates to a method for fabricating a semicon ductor Substrate by providing a
silicon on insulator type Sub strate that includes a base, an insulating layer and a first …
silicon on insulator type Sub strate that includes a base, an insulating layer and a first …
[PDF][PDF] Through Silicon Via Field-Effect Transistor with Hafnia-based Ferroelectrics and the Do** of Silicon by Gallium Implantation Utilizing a Focused Ion Beam …
F Winkler - 2020 - core.ac.uk
Die 3-dimensionale Integration hat sich zur weiteren Erhöhung der Transistordichte und der
integrierten Funktionalität in Mikrochips als ein Standard durchgesetzt. Integrierte …
integrierten Funktionalität in Mikrochips als ein Standard durchgesetzt. Integrierte …
CV do** profiling of boron out-diffusion using an abrupt and highly doped arsenic buried epilayer
The use of CV measurements to profile the electrically active impurity profile of dopants has
long been popular as a fast and non-destructive measurement technique. In this work, an …
long been popular as a fast and non-destructive measurement technique. In this work, an …