Apparatuses and methods are provided for reversing data stored in memory. An example
apparatus comprises an array of memory cells, a first plurality of sensing components …

(51) Int. Cl. 6,301,153 B1 10/2001 Takeuchi et al. GIIC5/06(2006.01) 6,301,164 B1 10/2001
Manning et al. 6,304,477 B1 10/2001 Naji GIC II/4096(2006.01) 6,389,507 B1 5/2002 …

Examples of the present disclosure provide apparatuses and methods for target architecture
determination. An example method comprises receiving an indication of a type of target …

The present disclosure includes apparatus and methods for debugging on a memory device.
An example apparatus comprises a memory device having an array of memory cells and …

The present disclosure includes apparatuses and methods for operations using compressed
and decompressed data. An example method includes receiving compressed data to a …

5,367.488 A 11/1994 An 7,372,715 B2 5, 2008 Han 5,379,257 A 1/1995 Matsumura et al.
7,400,532 B2 7/2008 Aritome 5,386,379 A 1/1995 Ali-Yahia et al. 7.406, 494 B2 7/2008 …

The present disclosure includes apparatuses and methods for data movement. An example
apparatus includes a memory device that includes a plurality of subarrays of memory cells …

The present disclosure includes apparatus and methods for debugging on a host and
memory device. An example apparatus comprises a memory device having an array of …

The present disclosure includes apparatuses and methods related to performing corner turn
operations using sensing circuitry. An example apparatus comprises a first group of memory …

The present disclosure includes apparatuses and methods for cache invalidate. An example
apparatus comprises a bit vector capable memory device and a channel controller coupled …