This paper aims to explore diverse landscape of Phase Locked Loops (PLLs), offering a
comprehensive categorization and in-depth analysis of their underlying working principles …

An analog fractional-sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-
detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In …

This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …

5G is the latest global wireless standard, known as the fifth generation of cellular mobile
communication technology. Compared to 4G LTE, 5G increases peak data rates and …

As new applications impose jitter values in the range of a few tens of femtoseconds, the
design of phase-locked loops faces daunting challenges. This paper derives basic relations …

This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …

This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …

This paper presents phase-locked loop (PLL) reference-spur reduction design techniques
exploiting a sub-sampling phase detector (SSPD)(which is also referred to as a sampling …

A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider
to achieve low in-band noise with a wide bandwidth is presented. The fractional divider …